console.log

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

Design: 9:04 PM, Tuesday, March 31, 2009
Design: Opening design "c:\my designs\decoder\decoder.adf"
Design: Error: C:\My Designs\decoder\src\VHDL code2.vhd cannot be compiled.
Compilation...
File: .\src\VHDL code2.vhd
Compile Entity "dec24d"
Compile Architecture "dataflow" of Entity "dec24d"
Compile success 0 Errors 0 Warnings  Analysis time :  0.0 [s]
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
KERNEL: Main thread initiated.
KERNEL: Kernel process initialization phase.
ELAB2: Elaboration final pass...
ELAB2: Elaboration final pass complete - time: 0.0 [s].
KERNEL: Kernel process initialization done.
9:05 PM, Tuesday, March 31, 2009
Simulation has been initialized
Selected Top-Level: dec24d (dataflow)
Cannot force signal A with formula 0 0, 1 100000 -r 200000.
Cannot force signal A with formula 0 0, 1 100000 -r 200000.
Cannot force signal A with formula 0 0, 1 50000 -r 100000.
Cannot force signal A with formula 0 0, 1 1600000 -r 3200000.
Cannot force signal A with formula 0 0, 1 3200000 -r 6400000.
Cannot force signal A with formula 0 0, 1 6400000 -r 12800000.
Cannot force signal A with formula 0 0, 1 800000 -r 1600000.
Cannot force signal A with formula 0 0, 1 400000 -r 800000.
Simulation has been stopped