compile.log

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

 Compilation...
 File: .\src\VHDL code1.vhd
Error:  COMP96_0016:VHDL code1.vhd : (1, 1): Design unit declaration expected.
Error:  COMP96_0016:VHDL code1.vhd : (2, 14): Design unit declaration expected.
Error:  COMP96_0016:VHDL code1.vhd : (2, 15): Design unit declaration expected.
Error:  COMP96_0018:VHDL code1.vhd : (3, 1): Identifier expected.
Error:  COMP96_0016:VHDL code1.vhd : (3, 5): Design unit declaration expected.
Error:  COMP96_0016:VHDL code1.vhd : (3, 9): Design unit declaration expected.
Error:  COMP96_0018:VHDL code1.vhd : (3, 52): Identifier expected.
Error:  COMP96_0016:VHDL code1.vhd : (4, 1): Design unit declaration expected.
 Compile Entity "declaration"
Error:  COMP96_0019:VHDL code1.vhd : (4, 21): Keyword "is" expected.
Error:  COMP96_0019:VHDL code1.vhd : (4, 21): Keyword "end" expected.
Error:  COMP96_0015:VHDL code1.vhd : (4, 21): ';' expected.
 Compile Entity "comp4b"
Error:  COMP96_0019:VHDL code1.vhd : (7, 21): Keyword "end" expected.
Error:  COMP96_0015:VHDL code1.vhd : (7, 21): ';' expected.
Error:  COMP96_0016:VHDL code1.vhd : (7, 22): Design unit declaration expected.
Error:  COMP96_0018:VHDL code1.vhd : (8, 11): Identifier expected.
Error:  COMP96_0016:VHDL code1.vhd : (8, 13): Design unit declaration expected.
 Compile Entity "declaration"
Error:  COMP96_0019:VHDL code1.vhd : (8, 41): Keyword "is" expected.
Error:  COMP96_0019:VHDL code1.vhd : (8, 41): Keyword "end" expected.
Error:  COMP96_0015:VHDL code1.vhd : (8, 41): ';' expected.
 Compile Architecture "behav" of Entity "comp4b"
Error:  COMP96_0019:VHDL code1.vhd : (11, 14): Keyword "begin" expected.
Error:  COMP96_0019:VHDL code1.vhd : (11, 14): Keyword "end" expected.
Error:  COMP96_0019:VHDL code1.vhd : (11, 14): Keyword "process" expected.
Error:  COMP96_0015:VHDL code1.vhd : (11, 14): ';' expected.
Error:  COMP96_0019:VHDL code1.vhd : (11, 14): Keyword "end" expected.
Error:  COMP96_0015:VHDL code1.vhd : (11, 14): ';' expected.
Error:  COMP96_0016:VHDL code1.vhd : (11, 15): Design unit declaration expected.
Error:  COMP96_0018:VHDL code1.vhd : (31, 34): Identifier expected.
 Compile failure 27 Errors 0 Warnings  Analysis time :  0.0 [s]
 Compilation...
 File: .\src\VHDL code1.vhd
 Compile Entity "comp4b"
 Compile Architecture "behav" of Entity "comp4b"
 Compile success 0 Errors 0 Warnings  Analysis time :  0.1 [s]