mod5.erf

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

MESSAGE "File: .\src\VHDL code1.vhd" 
MESSAGE "Compile Entity "ffT"" 
MESSAGE "Entity "ffT" has been skipped - no difference detected." 
MESSAGE "Compile Architecture "behav" of Entity "ffT"" 
MESSAGE "Compile Entity "AND2"" 
MESSAGE "Entity "AND2" has been skipped - no difference detected." 
MESSAGE "Compile Architecture "behav1" of Entity "AND2"" 
MESSAGE "Compile Entity "OR2"" 
MESSAGE "Entity "OR2" has been skipped - no difference detected." 
MESSAGE "Compile Architecture "behav2" of Entity "OR2"" 
MESSAGE "Compile Entity "mod5"" 
MESSAGE "Entity "mod5" has been skipped - no difference detected." 
MESSAGE "Compile Architecture "structure" of Entity "mod5"" 
ERROR COMP96_0100: "Port types or modes of actuals in component instantiation do not match those in component declaration." "C:\My Designs\mod5\src\VHDL code1.vhd" 68 20
ERROR COMP96_0100: "Port types or modes of actuals in component instantiation do not match those in component declaration." "C:\My Designs\mod5\src\VHDL code1.vhd" 68 28
ERROR COMP96_0100: "Port types or modes of actuals in component instantiation do not match those in component declaration." "C:\My Designs\mod5\src\VHDL code1.vhd" 69 20
ERROR COMP96_0100: "Port types or modes of actuals in component instantiation do not match those in component declaration." "C:\My Designs\mod5\src\VHDL code1.vhd" 71 34
ERROR COMP96_0100: "Port types or modes of actuals in component instantiation do not match those in component declaration." "C:\My Designs\mod5\src\VHDL code1.vhd" 72 34
MESSAGE "Compile failure 5 Errors 0 Warnings  Analysis time :  0.1 [s]"