compile.log

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

 Compilation...
 File: .\src\VHDL code1.vhd
 Compile Entity "ffT"
 Entity "ffT" has been skipped - no difference detected.
 Compile Architecture "behav" of Entity "ffT"
 Compile Entity "AND2"
 Entity "AND2" has been skipped - no difference detected.
 Compile Architecture "behav1" of Entity "AND2"
 Compile Entity "OR2"
 Entity "OR2" has been skipped - no difference detected.
 Compile Architecture "behav2" of Entity "OR2"
 Compile Entity "mod5"
 Entity "mod5" has been skipped - no difference detected.
 Compile Architecture "structure" of Entity "mod5"
Error:  COMP96_0100:VHDL code1.vhd : (68, 20): Port types or modes of actuals in component instantiation do not match those in component declaration.
Error:  COMP96_0100:VHDL code1.vhd : (68, 28): Port types or modes of actuals in component instantiation do not match those in component declaration.
Error:  COMP96_0100:VHDL code1.vhd : (69, 20): Port types or modes of actuals in component instantiation do not match those in component declaration.
Error:  COMP96_0100:VHDL code1.vhd : (71, 34): Port types or modes of actuals in component instantiation do not match those in component declaration.
Error:  COMP96_0100:VHDL code1.vhd : (72, 34): Port types or modes of actuals in component instantiation do not match those in component declaration.
 Compile failure 5 Errors 0 Warnings  Analysis time :  0.1 [s]