📄 lichengji1.rpt
字号:
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kechengsheji\lichengji1.rpt
lichengji1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: f:\kechengsheji\lichengji1.rpt
lichengji1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 18 reset
Device-Specific Information: f:\kechengsheji\lichengji1.rpt
lichengji1
** EQUATIONS **
clk : INPUT;
reset : INPUT;
stop : INPUT;
-- Node name is 'en'
-- Equation name is 'en', type is output
en = _LC8_A16;
-- Node name is ':21' = 'ge0'
-- Equation name is 'ge0', location is LC6_A24, type is buried.
ge0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !ge0 & !stop
# ge0 & stop;
-- Node name is 'ge_00'
-- Equation name is 'ge_00', type is output
ge_00 = _LC6_A22;
-- Node name is ':20' = 'ge1'
-- Equation name is 'ge1', location is LC2_A24, type is buried.
ge1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = !ge0 & ge1 & !_LC3_A22
# ge0 & !ge1 & !_LC3_A22 & !stop
# ge1 & stop;
-- Node name is 'ge_01'
-- Equation name is 'ge_01', type is output
ge_01 = _LC1_A24;
-- Node name is ':19' = 'ge2'
-- Equation name is 'ge2', location is LC7_A24, type is buried.
ge2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !_LC3_A22 & _LC8_A24 & !stop
# ge2 & stop;
-- Node name is 'ge_02'
-- Equation name is 'ge_02', type is output
ge_02 = _LC4_A24;
-- Node name is ':18' = 'ge3'
-- Equation name is 'ge3', location is LC8_A22, type is buried.
ge3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = ge3 & !_LC3_A22 & !_LC5_A24
# !ge3 & !_LC3_A22 & _LC5_A24 & !stop
# ge3 & stop;
-- Node name is 'ge_03'
-- Equation name is 'ge_03', type is output
ge_03 = _LC5_A22;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_A16, type is buried.
-- synthesized logic cell
!_LC1_A16 = _LC1_A16~NOT;
_LC1_A16~NOT = LCELL(!reset);
-- Node name is ':17' = 'shi0'
-- Equation name is 'shi0', location is LC3_A24, type is buried.
shi0 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !_LC3_A22 & shi0
# _LC3_A22 & !shi0 & !stop
# shi0 & stop;
-- Node name is ':16' = 'shi1'
-- Equation name is 'shi1', location is LC4_A13, type is buried.
shi1 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = _LC5_A13 & !stop
# !_LC3_A22 & shi1
# shi1 & stop;
-- Node name is ':15' = 'shi2'
-- Equation name is 'shi2', location is LC2_A13, type is buried.
shi2 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = _LC6_A13 & !stop
# !_LC3_A22 & shi2
# shi2 & stop;
-- Node name is ':14' = 'shi3'
-- Equation name is 'shi3', location is LC3_A13, type is buried.
shi3 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = _LC8_A13 & !stop
# !_LC3_A22 & shi3
# shi3 & stop;
-- Node name is 'shi_10'
-- Equation name is 'shi_10', type is output
shi_10 = _LC1_A22;
-- Node name is 'shi_11'
-- Equation name is 'shi_11', type is output
shi_11 = _LC2_A2;
-- Node name is 'shi_12'
-- Equation name is 'shi_12', type is output
shi_12 = _LC3_A17;
-- Node name is 'shi_13'
-- Equation name is 'shi_13', type is output
shi_13 = _LC8_A21;
-- Node name is '|LPM_ADD_SUB:159|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ009);
_EQ009 = shi0 & shi1;
-- Node name is '|LPM_ADD_SUB:218|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ010);
_EQ010 = ge0 & ge1 & ge2;
-- Node name is '|LPM_ADD_SUB:218|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ011);
_EQ011 = !ge1 & ge2
# !ge0 & ge2
# ge0 & ge1 & !ge2;
-- Node name is ':4'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, !_LC1_A16);
_EQ012 = _LC8_A16
# _LC4_A22;
-- Node name is ':116'
-- Equation name is '_LC3_A22', type is buried
!_LC3_A22 = _LC3_A22~NOT;
_LC3_A22~NOT = LCELL( _EQ013);
_EQ013 = ge2
# !ge3
# ge1
# !ge0;
-- Node name is ':134'
-- Equation name is '_LC1_A13', type is buried
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( _EQ014);
_EQ014 = shi2
# shi1
# !shi3
# !shi0;
-- Node name is '~261~1'
-- Equation name is '~261~1', location is LC2_A22, type is buried.
-- synthesized logic cell
_LC2_A22 = LCELL( _EQ015);
_EQ015 = !_LC1_A13 & _LC3_A22;
-- Node name is ':261'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ016);
_EQ016 = _LC2_A22 & !_LC7_A13 & shi3
# _LC2_A22 & !shi2 & shi3
# _LC2_A22 & _LC7_A13 & shi2 & !shi3;
-- Node name is ':267'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ017);
_EQ017 = _LC2_A22 & !shi1 & shi2
# _LC2_A22 & !shi0 & shi2
# _LC2_A22 & shi0 & shi1 & !shi2;
-- Node name is ':273'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ018);
_EQ018 = _LC2_A22 & !shi0 & shi1
# _LC2_A22 & shi0 & !shi1;
-- Node name is ':285'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = LCELL( _EQ019);
_EQ019 = ge0 & ge1 & !ge2 & !ge3;
-- Node name is ':608'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = LCELL( _EQ020);
_EQ020 = _LC5_A22 & reset
# ge3 & _LC7_A22;
-- Node name is ':614'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ021);
_EQ021 = _LC4_A24 & reset
# ge2 & !reset;
-- Node name is ':620'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ022);
_EQ022 = _LC1_A24 & reset
# ge1 & !reset;
-- Node name is ':626'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ023);
_EQ023 = _LC6_A22 & reset
# ge0 & _LC7_A22;
-- Node name is '~628~1'
-- Equation name is '~628~1', location is LC7_A22, type is buried.
-- synthesized logic cell
_LC7_A22 = LCELL( _EQ024);
_EQ024 = !_LC1_A13 & !reset
# !_LC3_A22 & !reset;
-- Node name is ':632'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ025);
_EQ025 = _LC8_A21 & reset
# _LC7_A22 & shi3;
-- Node name is ':638'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = LCELL( _EQ026);
_EQ026 = _LC3_A17 & reset
# !reset & shi2;
-- Node name is ':644'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ027);
_EQ027 = _LC2_A2 & reset
# !reset & shi1;
-- Node name is ':650'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ028);
_EQ028 = _LC1_A22 & reset
# _LC7_A22 & shi0;
Project Information f:\kechengsheji\lichengji1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,396K
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