select48.rpt

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RPT
780
字号
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                               f:\sss\select48.rpt
select48

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      8     -    A    24       AND2                3    0    0    4  :107
   -      1     -    A    19       AND2                3    0    0    4  :114
   -      2     -    A    19       AND2                3    0    0    4  :121
   -      8     -    A    19       AND2                3    0    0    4  :128
   -      2     -    A    21       AND2                3    0    0    4  :135
   -      3     -    A    21       AND2                3    0    0    4  :142
   -      4     -    A    21       AND2                3    0    0    4  :149
   -      3     -    A    20       AND2                4    0    0    1  :298
   -      2     -    A    20        OR2                3    1    0    1  :299
   -      4     -    A    20        OR2                1    3    0    1  :303
   -      5     -    A    20        OR2                1    2    0    1  :309
   -      6     -    A    20        OR2                1    2    0    1  :315
   -      7     -    A    20        OR2                1    2    0    1  :321
   -      8     -    A    20        OR2                1    2    0    1  :327
   -      1     -    A    20        OR2                1    2    0    1  :333
   -      1     -    A    24        OR2                1    2    1    1  :339
   -      3     -    A    14       AND2                4    0    0    1  :346
   -      2     -    A    14        OR2                3    1    0    1  :347
   -      4     -    A    14        OR2                1    3    0    1  :348
   -      5     -    A    14        OR2                1    2    0    1  :351
   -      6     -    A    14        OR2                1    2    0    1  :354
   -      7     -    A    14        OR2                1    2    0    1  :357
   -      8     -    A    14        OR2                1    2    0    1  :360
   -      1     -    A    14        OR2                1    2    0    1  :363
   -      2     -    A    24        OR2                1    2    1    1  :366
   -      2     -    A    22       AND2                4    0    0    1  :373
   -      1     -    A    22        OR2                3    1    0    1  :374
   -      3     -    A    22        OR2                1    3    0    1  :375
   -      4     -    A    22        OR2                1    2    0    1  :378
   -      5     -    A    22        OR2                1    2    0    1  :381
   -      6     -    A    22        OR2                1    2    0    1  :384
   -      7     -    A    22        OR2                1    2    0    1  :387
   -      8     -    A    22        OR2                1    2    0    1  :390
   -      7     -    A    24        OR2                1    2    1    1  :393
   -      6     -    A    21       AND2                4    0    0    1  :400
   -      5     -    A    21        OR2                3    1    0    1  :401
   -      7     -    A    21        OR2                1    3    0    1  :402
   -      8     -    A    21        OR2                1    2    0    1  :405
   -      1     -    A    21        OR2                1    2    0    1  :408
   -      3     -    A    24        OR2                1    2    0    1  :411
   -      5     -    A    24        OR2                1    2    0    1  :414
   -      6     -    A    24        OR2                1    2    0    1  :417
   -      4     -    A    24        OR2                1    2    1    1  :420


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                               f:\sss\select48.rpt
select48

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      24/ 96( 25%)     0/ 48(  0%)    19/ 48( 39%)    5/16( 31%)      4/16( 25%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
12:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                               f:\sss\select48.rpt
select48

** EQUATIONS **

d00      : INPUT;
d01      : INPUT;
d02      : INPUT;
d03      : INPUT;
d10      : INPUT;
d11      : INPUT;
d12      : INPUT;
d13      : INPUT;
d20      : INPUT;
d21      : INPUT;
d22      : INPUT;
d23      : INPUT;
d30      : INPUT;
d31      : INPUT;
d32      : INPUT;
d33      : INPUT;
d40      : INPUT;
d41      : INPUT;
d42      : INPUT;
d43      : INPUT;
d50      : INPUT;
d51      : INPUT;
d52      : INPUT;
d53      : INPUT;
d60      : INPUT;
d61      : INPUT;
d62      : INPUT;
d63      : INPUT;
d70      : INPUT;
d71      : INPUT;
d72      : INPUT;
d73      : INPUT;
sel0     : INPUT;
sel1     : INPUT;
sel2     : INPUT;

-- Node name is 'y0' 
-- Equation name is 'y0', type is output 
y0       =  _LC1_A24;

-- Node name is 'y1' 
-- Equation name is 'y1', type is output 
y1       =  _LC2_A24;

-- Node name is 'y2' 
-- Equation name is 'y2', type is output 
y2       =  _LC7_A24;

-- Node name is 'y3' 
-- Equation name is 'y3', type is output 
y3       =  _LC4_A24;

-- Node name is ':107' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = LCELL( _EQ001);
  _EQ001 = !sel0 & !sel1 & !sel2;

-- Node name is ':114' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ002);
  _EQ002 = !sel0 & !sel1 &  sel2;

-- Node name is ':121' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = LCELL( _EQ003);
  _EQ003 = !sel0 &  sel1 & !sel2;

-- Node name is ':128' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ004);
  _EQ004 = !sel0 &  sel1 &  sel2;

-- Node name is ':135' 
-- Equation name is '_LC2_A21', type is buried 
_LC2_A21 = LCELL( _EQ005);
  _EQ005 =  sel0 & !sel1 & !sel2;

-- Node name is ':142' 
-- Equation name is '_LC3_A21', type is buried 
_LC3_A21 = LCELL( _EQ006);
  _EQ006 =  sel0 & !sel1 &  sel2;

-- Node name is ':149' 
-- Equation name is '_LC4_A21', type is buried 
_LC4_A21 = LCELL( _EQ007);
  _EQ007 =  sel0 &  sel1 & !sel2;

-- Node name is ':298' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ008);
  _EQ008 =  d70 &  sel0 &  sel1 &  sel2;

-- Node name is ':299' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ009);
  _EQ009 =  _LC1_A24 & !sel1
         #  _LC1_A24 & !sel2
         #  _LC1_A24 & !sel0;

-- Node name is ':303' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ010);
  _EQ010 =  _LC2_A20 & !_LC4_A21
         #  _LC3_A20 & !_LC4_A21
         #  d60 &  _LC4_A21;

-- Node name is ':309' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ011);
  _EQ011 = !_LC3_A21 &  _LC4_A20
         #  d50 &  _LC3_A21;

-- Node name is ':315' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ012);
  _EQ012 = !_LC2_A21 &  _LC5_A20
         #  d40 &  _LC2_A21;

-- Node name is ':321' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ013);
  _EQ013 =  _LC6_A20 & !_LC8_A19
         #  d30 &  _LC8_A19;

-- Node name is ':327' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ014);
  _EQ014 = !_LC2_A19 &  _LC7_A20
         #  d20 &  _LC2_A19;

-- Node name is ':333' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ015);
  _EQ015 = !_LC1_A19 &  _LC8_A20
         #  d10 &  _LC1_A19;

-- Node name is ':339' 
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = LCELL( _EQ016);
  _EQ016 =  _LC1_A20 & !_LC8_A24

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