zong.rpt
来自「出租车的计费系统」· RPT 代码 · 共 1,349 行 · 第 1/5 页
RPT
1,349 行
Total flipflops required: 55
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 11/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 4 8 8 8 8 8 8 8 3 0 7 0 0 0 0 0 0 1 1 8 0 0 104/0
B: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
C: 0 0 0 0 8 8 1 0 8 5 8 8 0 0 0 0 0 8 3 7 0 0 0 0 0 64/0
Total: 8 8 8 4 16 16 9 8 16 13 17 11 0 7 0 0 0 8 3 7 1 1 8 0 0 169/0
Device-Specific Information: f:\kechengsheji\zong.rpt
zong
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 cp1
43 - - - -- INPUT G 0 0 0 0 cp2
44 - - - -- INPUT 0 0 0 1 reset
61 - - C -- INPUT 0 0 0 1 speed1
62 - - C -- INPUT 0 0 0 1 speed2
84 - - - -- INPUT 0 0 0 1 speed3
2 - - - -- INPUT G 0 0 0 12 start
42 - - - -- INPUT 0 0 0 1 stop
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\kechengsheji\zong.rpt
zong
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- OUTPUT 0 1 0 0 l0
29 - - C -- OUTPUT 0 1 0 0 l1
60 - - C -- OUTPUT 0 1 0 0 l2
7 - - - 03 OUTPUT 0 1 0 0 l3
27 - - C -- OUTPUT 0 1 0 0 l4
17 - - A -- OUTPUT 0 1 0 0 l5
16 - - A -- OUTPUT 0 1 0 0 l6
8 - - - 03 OUTPUT 0 1 0 0 l7
83 - - - 13 OUTPUT 0 1 0 0 y0
47 - - - 14 OUTPUT 0 1 0 0 y1
69 - - A -- OUTPUT 0 1 0 0 y2
70 - - A -- OUTPUT 0 1 0 0 y3
71 - - A -- OUTPUT 0 1 0 0 y4
72 - - A -- OUTPUT 0 1 0 0 y5
24 - - B -- OUTPUT 0 1 0 0 y6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\kechengsheji\zong.rpt
zong
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 09 AND2 0 2 0 2 |BUFU1:12|LPM_ADD_SUB:132|addcore:adder|:55
- 4 - C 05 AND2 0 2 0 1 |BUFU1:12|LPM_ADD_SUB:191|addcore:adder|:55
- 6 - C 05 AND2 0 3 0 1 |BUFU1:12|LPM_ADD_SUB:191|addcore:adder|:59
- 7 - C 05 DFFE 0 4 0 9 |BUFU1:12|:4
- 8 - C 05 DFFE 0 5 0 1 |BUFU1:12|shi3 (|BUFU1:12|:6)
- 5 - C 05 DFFE 0 5 0 2 |BUFU1:12|shi2 (|BUFU1:12|:7)
- 3 - C 05 DFFE 0 5 0 3 |BUFU1:12|shi1 (|BUFU1:12|:8)
- 2 - C 05 DFFE 0 3 0 4 |BUFU1:12|shi0 (|BUFU1:12|:9)
- 8 - C 09 DFFE 0 5 0 2 |BUFU1:12|bai3 (|BUFU1:12|:10)
- 5 - C 09 DFFE 0 5 0 3 |BUFU1:12|bai2 (|BUFU1:12|:11)
- 1 - C 10 DFFE 0 5 0 3 |BUFU1:12|bai1 (|BUFU1:12|:12)
- 4 - C 09 DFFE 0 4 0 3 |BUFU1:12|bai0 (|BUFU1:12|:13)
- 1 - C 05 OR2 ! 0 4 0 11 |BUFU1:12|:89
- 2 - C 09 OR2 ! 0 4 0 4 |BUFU1:12|:107
- 6 - C 09 AND2 s 0 2 0 1 |BUFU1:12|~234~1
- 7 - C 09 OR2 0 4 0 1 |BUFU1:12|:234
- 3 - C 09 OR2 0 4 0 1 |BUFU1:12|:240
- 2 - C 10 OR2 0 4 0 1 |BUFU1:12|:246
- 4 - C 17 AND2 0 2 0 4 |CONTROL:15|LPM_ADD_SUB:81|addcore:adder|:79
- 7 - C 17 AND2 0 2 0 1 |CONTROL:15|LPM_ADD_SUB:81|addcore:adder|:83
- 1 - C 17 AND2 0 4 0 4 |CONTROL:15|LPM_ADD_SUB:81|addcore:adder|:91
- 4 - C 19 AND2 0 2 0 1 |CONTROL:15|LPM_ADD_SUB:81|addcore:adder|:95
- 6 - C 19 AND2 0 4 0 2 |CONTROL:15|LPM_ADD_SUB:81|addcore:adder|:103
- 1 - C 18 DFFE + 1 2 0 15 |CONTROL:15|:8
- 2 - C 19 DFFE + 1 2 0 1 |CONTROL:15|q9 (|CONTROL:15|:12)
- 7 - C 19 DFFE + 1 1 0 1 |CONTROL:15|q8 (|CONTROL:15|:13)
- 5 - C 19 DFFE + 1 2 0 1 |CONTROL:15|q7 (|CONTROL:15|:14)
- 3 - C 19 DFFE + 1 2 0 2 |CONTROL:15|q6 (|CONTROL:15|:15)
- 1 - C 19 DFFE + 1 1 0 3 |CONTROL:15|q5 (|CONTROL:15|:16)
- 8 - C 17 DFFE + 1 2 0 1 |CONTROL:15|q4 (|CONTROL:15|:17)
- 6 - C 17 DFFE + 1 2 0 2 |CONTROL:15|q3 (|CONTROL:15|:18)
- 5 - C 17 DFFE + 1 1 0 3 |CONTROL:15|q2 (|CONTROL:15|:19)
- 2 - C 17 DFFE + 1 1 0 2 |CONTROL:15|q1 (|CONTROL:15|:20)
- 3 - C 17 DFFE + 1 0 0 3 |CONTROL:15|q0 (|CONTROL:15|:21)
- 2 - C 18 OR2 1 2 0 1 |CONTROL:15|:256
- 3 - C 18 OR2 1 2 0 1 |CONTROL:15|:269
- 1 - C 07 OR2 ! 2 0 0 50 |CONTROL:15|:437
- 6 - A 07 OR2 s 0 4 0 2 |CONTROL:15|~443~1
- 2 - B 11 AND2 2 0 0 38 |CONTROL:15|:443
- 8 - A 03 OR2 0 3 1 0 |dongxian:1|LX8:3|:306
- 6 - A 03 DFFE + 0 2 0 9 |dongxian:1|M8:4|qo2 (|dongxian:1|M8:4|:6)
- 2 - A 03 DFFE + 0 1 0 10 |dongxian:1|M8:4|qo1 (|dongxian:1|M8:4|:7)
- 1 - A 21 DFFE + 0 0 0 11 |dongxian:1|M8:4|qo0 (|dongxian:1|M8:4|:8)
- 6 - A 10 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:107
- 5 - A 03 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:114
- 4 - A 03 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:121
- 7 - A 03 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:128
- 1 - A 03 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:135
- 3 - A 03 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:142
- 1 - A 10 AND2 0 3 1 4 |dongxian:1|SELECT48:1|:149
- 3 - A 10 AND2 0 3 0 4 |dongxian:1|SELECT48:1|:156
- 2 - A 01 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:297
- 3 - A 01 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:303
- 5 - A 01 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:309
- 6 - A 01 OR2 0 4 0 1 |dongxian:1|SELECT48:1|:321
- 7 - A 01 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:327
- 8 - A 01 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:333
- 1 - A 01 OR2 0 3 0 8 |dongxian:1|SELECT48:1|:339
- 2 - A 12 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:345
- 3 - A 12 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:348
- 1 - A 12 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:351
- 6 - C 06 OR2 0 4 0 1 |dongxian:1|SELECT48:1|:357
- 1 - C 06 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:360
- 8 - A 06 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:363
- 4 - A 06 OR2 0 3 0 8 |dongxian:1|SELECT48:1|:366
- 7 - A 10 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:372
- 8 - A 10 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:375
- 2 - A 10 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:378
- 2 - C 06 OR2 0 4 0 1 |dongxian:1|SELECT48:1|:384
- 4 - C 10 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:387
- 7 - C 10 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:390
- 5 - A 10 OR2 0 3 0 8 |dongxian:1|SELECT48:1|:393
- 3 - A 05 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:399
- 4 - A 05 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:402
- 5 - A 05 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:405
- 7 - A 05 OR2 0 4 0 1 |dongxian:1|SELECT48:1|:411
- 8 - A 05 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:414
- 1 - A 05 OR2 0 3 0 1 |dongxian:1|SELECT48:1|:417
- 2 - A 04 OR2 0 3 0 8 |dongxian:1|SELECT48:1|:420
- 6 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:383
- 3 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:416
- 4 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:449
- 5 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:482
- 8 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:515
- 1 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:548
- 7 - A 13 OR2 0 4 1 0 |dongxian:1|VB48:2|:583
- 3 - C 11 AND2 0 2 0 1 |LICHENGJI0:14|LPM_ADD_SUB:66|addcore:adder|:55
- 4 - C 11 AND2 0 3 0 1 |LICHENGJI0:14|LPM_ADD_SUB:66|addcore:adder|:59
- 1 - C 11 DFFE 0 3 0 9 |LICHENGJI0:14|:4
- 5 - C 11 DFFE 0 5 0 2 |LICHENGJI0:14|shifen3 (|LICHENGJI0:14|:10)
- 8 - C 11 DFFE 0 5 0 3 |LICHENGJI0:14|shifen2 (|LICHENGJI0:14|:11)
- 6 - C 11 DFFE 0 5 0 4 |LICHENGJI0:14|shifen1 (|LICHENGJI0:14|:12)
- 7 - C 11 DFFE 0 3 0 5 |LICHENGJI0:14|shifen0 (|LICHENGJI0:14|:13)
- 2 - C 11 OR2 ! 0 4 0 4 |LICHENGJI0:14|:75
- 6 - A 02 AND2 0 2 0 1 |LICHENGJI1:13|LPM_ADD_SUB:159|addcore:adder|:55
- 7 - A 08 AND2 0 3 0 1 |LICHENGJI1:13|LPM_ADD_SUB:218|addcore:adder|:59
- 5 - A 06 OR2 0 3 0 1 |LICHENGJI1:13|LPM_ADD_SUB:218|addcore:adder|:68
- 5 - A 08 DFFE 0 3 0 10 |LICHENGJI1:13|:4
- 3 - A 02 DFFE 0 5 0 3 |LICHENGJI1:13|shi3 (|LICHENGJI1:13|:14)
- 1 - A 02 DFFE 0 5 0 4 |LICHENGJI1:13|shi2 (|LICHENGJI1:13|:15)
- 2 - A 02 DFFE 0 5 0 5 |LICHENGJI1:13|shi1 (|LICHENGJI1:13|:16)
- 5 - A 04 DFFE 0 4 0 5 |LICHENGJI1:13|shi0 (|LICHENGJI1:13|:17)
- 8 - A 08 DFFE 0 5 0 3 |LICHENGJI1:13|ge3 (|LICHENGJI1:13|:18)
- 3 - A 06 DFFE 0 5 0 5 |LICHENGJI1:13|ge2 (|LICHENGJI1:13|:19)
- 6 - A 08 DFFE 0 5 0 5 |LICHENGJI1:13|ge1 (|LICHENGJI1:13|:20)
- 3 - A 08 DFFE 0 3 0 6 |LICHENGJI1:13|ge0 (|LICHENGJI1:13|:21)
- 1 - A 08 OR2 ! 0 4 0 9 |LICHENGJI1:13|:116
- 8 - A 02 OR2 ! 0 4 0 2 |LICHENGJI1:13|:134
- 1 - A 06 AND2 s 0 2 0 3 |LICHENGJI1:13|~261~1
- 7 - A 02 OR2 0 4 0 1 |LICHENGJI1:13|:261
- 5 - A 02 OR2 0 4 0 1 |LICHENGJI1:13|:267
- 4 - A 02 OR2 0 3 0 1 |LICHENGJI1:13|:273
- 2 - A 08 AND2 0 4 0 1 |LICHENGJI1:13|:285
- 4 - A 08 OR2 0 3 0 1 |LICHENGJI1:13|:608
- 6 - A 06 OR2 0 2 0 1 |LICHENGJI1:13|:614
- 3 - C 10 OR2 0 2 0 1 |LICHENGJI1:13|:620
- 2 - A 05 OR2 0 3 0 1 |LICHENGJI1:13|:626
- 1 - A 04 OR2 0 3 0 1 |LICHENGJI1:13|:632
- 2 - A 06 OR2 s 0 3 0 4 |LICHENGJI1:13|~634~1
- 7 - A 06 OR2 0 2 0 1 |LICHENGJI1:13|:638
- 4 - A 10 OR2 0 2 0 1 |LICHENGJI1:13|:644
- 3 - A 04 OR2 0 3 0 1 |LICHENGJI1:13|:650
- 7 - A 11 AND2 0 2 0 1 |XIAOSH:10|LPM_ADD_SUB:297|addcore:adder|:55
- 5 - A 09 AND2 0 2 0 1 |XIAOSH:10|LPM_ADD_SUB:306|addcore:adder|:55
- 4 - A 11 DFFE 0 4 0 9 |XIAOSH:10|:6
- 8 - A 09 DFFE 0 5 0 4 |XIAOSH:10|shifen3 (|XIAOSH:10|:16)
- 3 - A 09 DFFE 0 5 0 4 |XIAOSH:10|shifen2 (|XIAOSH:10|:17)
- 4 - A 09 DFFE 0 5 0 5 |XIAOSH:10|shifen1 (|XIAOSH:10|:18)
- 5 - A 07 DFFE 0 5 0 6 |XIAOSH:10|shifen0 (|XIAOSH:10|:19)
- 6 - A 11 DFFE 0 5 0 4 |XIAOSH:10|baifen3 (|XIAOSH:10|:20)
- 2 - A 11 DFFE 0 5 0 5 |XIAOSH:10|baifen2 (|XIAOSH:10|:21)
- 2 - A 07 DFFE 0 5 0 6 |XIAOSH:10|baifen1 (|XIAOSH:10|:22)
- 8 - A 07 DFFE 0 5 0 6 |XIAOSH:10|baifen0 (|XIAOSH:10|:23)
- 4 - A 01 OR2 s 0 2 0 1 |XIAOSH:10|~173~1
- 3 - A 11 OR2 s 0 4 0 1 |XIAOSH:10|~173~2
- 1 - A 11 OR2 ! 0 4 0 2 |XIAOSH:10|:173
- 1 - A 07 AND2 ! 0 3 0 1 |XIAOSH:10|:355
- 6 - A 09 OR2 s ! 0 2 0 2 |XIAOSH:10|~376~1
- 3 - A 07 OR2 ! 0 4 0 2 |XIAOSH:10|:388
- 8 - A 11 OR2 0 4 0 1 |XIAOSH:10|:477
- 5 - A 11 OR2 0 4 0 1 |XIAOSH:10|:483
- 7 - A 07 OR2 s 0 3 0 6 |XIAOSH:10|~489~1
- 4 - A 07 OR2 0 3 0 1 |XIAOSH:10|:489
- 7 - A 09 OR2 0 4 0 1 |XIAOSH:10|:501
- 2 - A 09 OR2 0 4 0 1 |XIAOSH:10|:507
- 1 - A 09 OR2 0 3 0 1 |XIAOSH:10|:513
- 3 - C 06 AND2 0 2 0 1 |ZHENGSHU:11|LPM_ADD_SUB:167|addcore:adder|:55
- 8 - C 06 AND2 0 3 0 1 |ZHENGSHU:11|LPM_ADD_SUB:167|addcore:adder|:59
- 6 - A 22 AND2 0 2 0 1 |ZHENGSHU:11|LPM_ADD_SUB:226|addcore:adder|:55
- 2 - C 12 DFFE 0 4 0 2 |ZHENGSHU:11|:4
- 7 - C 12 DFFE 0 5 0 5 |ZHENGSHU:11|shi3 (|ZHENGSHU:11|:14)
- 5 - C 06 DFFE 0 5 0 4 |ZHENGSHU:11|shi2 (|ZHENGSHU:11|:15)
- 6 - C 12 DFFE 0 5 0 5 |ZHENGSHU:11|shi1 (|ZHENGSHU:11|:16)
- 3 - C 12 DFFE 0 5 0 6 |ZHENGSHU:11|shi0 (|ZHENGSHU:11|:17)
- 5 - A 22 DFFE 0 5 0 3 |ZHENGSHU:11|ge3 (|ZHENGSHU:11|:18)
- 1 - A 22 DFFE 0 5 0 4 |ZHENGSHU:11|ge2 (|ZHENGSHU:11|:19)
- 2 - A 22 DFFE 0 5 0 5 |ZHENGSHU:11|ge1 (|ZHENGSHU:11|:20)
- 6 - A 05 DFFE 0 4 0 5 |ZHENGSHU:11|ge0 (|ZHENGSHU:11|:21)
- 7 - A 22 OR2 ! 0 4 0 7 |ZHENGSHU:11|:124
- 5 - C 12 OR2 0 4 0 1 |ZHENGSHU:11|:268
- 1 - C 12 OR2 s 0 4 0 3 |ZHENGSHU:11|~269~1
- 4 - C 06 OR2 0 4 0 1 |ZHENGSHU:11|:274
- 4 - C 12 OR2 0 4 0 1 |ZHENGSHU:11|:280
- 7 - C 06 OR2 s 0 2 0 3 |ZHENGSHU:11|~321~1
- 2 - A 20 AND2 s 0 2 0 3 |ZHENGSHU:11|~392~1
- 8 - A 22 OR2 0 4 0 1 |ZHENGSHU:11|:392
- 4 - A 22 OR2 0 4 0 1 |ZHENGSHU:11|:398
- 3 - A 22 OR2 0 3 0 1 |ZHENGSHU:11|:404
- 8 - C 12 OR2 ! 0 4 0 8 |ZHENGSHU:11|:429
Code:
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