lichengji0.vhd

来自「出租车的计费系统」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lichengji0 is
    port(clk,reset,stop    :in std_logic;
         co           :out std_logic;
         shifen_1     :out std_logic_vector(3 downto 0));
end lichengji0;
architecture licheng_x of lichengji0 is
  signal shifen:std_logic_vector(3 downto 0); 
begin
    process(clk,reset,stop)
      begin
       if(reset='1') then
         shifen<="0000";
       else if(clk'event and clk='1') then
           shifen<=shifen+1;
             if(shifen=9) then
                 co<='1';
                 shifen<="0000";
              else
                 co<='0';
             end if;
            end if;
      end if;
      if(stop='1') then
         shifen<=shifen;
       end if;
    shifen_1<=shifen;
end process;
end licheng_x;