lx8.rpt
来自「出租车的计费系统」· RPT 代码 · 共 521 行 · 第 1/2 页
RPT
521 行
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\kechengsheji\lx8.rpt
lx8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kechengsheji\lx8.rpt
lx8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
g1 : INPUT;
g2a : INPUT;
g2b : INPUT;
-- Node name is 'l0'
-- Equation name is 'l0', type is output
l0 = _LC4_C17;
-- Node name is 'l1'
-- Equation name is 'l1', type is output
l1 = _LC5_C17;
-- Node name is 'l2'
-- Equation name is 'l2', type is output
l2 = _LC7_C17;
-- Node name is 'l3'
-- Equation name is 'l3', type is output
l3 = _LC3_C17;
-- Node name is 'l4'
-- Equation name is 'l4', type is output
l4 = _LC1_C17;
-- Node name is 'l5'
-- Equation name is 'l5', type is output
l5 = _LC6_C17;
-- Node name is 'l6'
-- Equation name is 'l6', type is output
l6 = _LC2_C17;
-- Node name is 'l7'
-- Equation name is 'l7', type is output
l7 = _LC8_C17;
-- Node name is ':101'
-- Equation name is '_LC1_C22', type is buried
!_LC1_C22 = _LC1_C22~NOT;
_LC1_C22~NOT = LCELL( _EQ001);
_EQ001 = !g1
# g2a
# g2b;
-- Node name is ':510'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = LCELL( _EQ002);
_EQ002 = !a2
# !a1
# !a0
# !_LC1_C22;
-- Node name is ':516'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = LCELL( _EQ003);
_EQ003 = !a1
# a0
# !a2
# !_LC1_C22;
-- Node name is ':522'
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = LCELL( _EQ004);
_EQ004 = a1
# !a0
# !a2
# !_LC1_C22;
-- Node name is ':528'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = LCELL( _EQ005);
_EQ005 = a1
# a0
# !a2
# !_LC1_C22;
-- Node name is ':534'
-- Equation name is '_LC3_C17', type is buried
_LC3_C17 = LCELL( _EQ006);
_EQ006 = !a1
# !a0
# a2
# !_LC1_C22;
-- Node name is ':540'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = LCELL( _EQ007);
_EQ007 = !a1
# a0
# a2
# !_LC1_C22;
-- Node name is ':546'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = LCELL( _EQ008);
_EQ008 = a1
# !a0
# a2
# !_LC1_C22;
-- Node name is ':552'
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ009);
_EQ009 = !_LC1_C22
# a2
# a1
# a0;
Project Information f:\kechengsheji\lx8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,369K
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