📄 zhengshu.rpt
字号:
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\mux\kechengsheji\zhengshu.rpt
zhengshu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\mux\kechengsheji\zhengshu.rpt
zhengshu
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 reset
Device-Specific Information: d:\mux\kechengsheji\zhengshu.rpt
zhengshu
** EQUATIONS **
clk : INPUT;
reset : INPUT;
stop : INPUT;
-- Node name is 'enn'
-- Equation name is 'enn', type is output
enn = _LC1_A9;
-- Node name is ':21' = 'ge0'
-- Equation name is 'ge0', location is LC4_A9, type is buried.
ge0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !ge0 & !_LC4_A1 & !stop
# ge0 & !_LC4_A1 & stop;
-- Node name is 'ge_00'
-- Equation name is 'ge_00', type is output
ge_00 = ge0;
-- Node name is ':20' = 'ge1'
-- Equation name is 'ge1', location is LC1_A2, type is buried.
ge1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = _LC2_A2 & !_LC4_A1
# ge1 & !_LC4_A1 & stop;
-- Node name is 'ge_01'
-- Equation name is 'ge_01', type is output
ge_01 = ge1;
-- Node name is ':19' = 'ge2'
-- Equation name is 'ge2', location is LC3_A2, type is buried.
ge2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !_LC4_A1 & _LC4_A2
# ge2 & !_LC4_A1 & stop;
-- Node name is 'ge_02'
-- Equation name is 'ge_02', type is output
ge_02 = ge2;
-- Node name is ':18' = 'ge3'
-- Equation name is 'ge3', location is LC6_A2, type is buried.
ge3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = !_LC4_A1 & _LC7_A2
# ge3 & !_LC4_A1 & stop;
-- Node name is 'ge_03'
-- Equation name is 'ge_03', type is output
ge_03 = ge3;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC8_A9, type is buried.
-- synthesized logic cell
!_LC8_A9 = _LC8_A9~NOT;
_LC8_A9~NOT = LCELL(!reset);
-- Node name is ':17' = 'shi0'
-- Equation name is 'shi0', location is LC1_A1, type is buried.
shi0 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !_LC4_A1 & !_LC8_A2 & shi0
# !_LC4_A1 & _LC8_A2 & !shi0 & !stop
# !_LC4_A1 & shi0 & stop;
-- Node name is ':16' = 'shi1'
-- Equation name is 'shi1', location is LC8_A1, type is buried.
shi1 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = !_LC4_A1 & _LC5_A1 & !stop
# !_LC4_A1 & shi1 & stop;
-- Node name is ':15' = 'shi2'
-- Equation name is 'shi2', location is LC5_A9, type is buried.
shi2 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC4_A1 & _LC7_A9 & !stop
# !_LC4_A1 & shi2 & stop;
-- Node name is ':14' = 'shi3'
-- Equation name is 'shi3', location is LC3_A1, type is buried.
shi3 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = !_LC4_A1 & _LC7_A1 & !stop
# !_LC4_A1 & shi3 & stop;
-- Node name is 'shi_10'
-- Equation name is 'shi_10', type is output
shi_10 = shi0;
-- Node name is 'shi_11'
-- Equation name is 'shi_11', type is output
shi_11 = shi1;
-- Node name is 'shi_12'
-- Equation name is 'shi_12', type is output
shi_12 = shi2;
-- Node name is 'shi_13'
-- Equation name is 'shi_13', type is output
shi_13 = shi3;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ009);
_EQ009 = shi0 & shi1;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ010);
_EQ010 = shi0 & shi1 & shi2;
-- Node name is '|LPM_ADD_SUB:226|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ011);
_EQ011 = ge0 & ge1;
-- Node name is ':4'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, !_LC8_A9);
_EQ012 = _LC1_A9
# shi3
# _LC6_A9;
-- Node name is ':124'
-- Equation name is '_LC8_A2', type is buried
!_LC8_A2 = _LC8_A2~NOT;
_LC8_A2~NOT = LCELL( _EQ013);
_EQ013 = ge2
# ge1
# !ge3
# !ge0;
-- Node name is '~142~1'
-- Equation name is '~142~1', location is LC6_A9, type is buried.
-- synthesized logic cell
_LC6_A9 = LCELL( _EQ014);
_EQ014 = shi2
# shi1;
-- Node name is ':268'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ015);
_EQ015 = _LC2_A1 & !_LC6_A1 & shi3
# _LC2_A1 & _LC6_A1 & !shi3
# !_LC8_A2 & shi3;
-- Node name is '~269~1'
-- Equation name is '~269~1', location is LC2_A1, type is buried.
-- synthesized logic cell
_LC2_A1 = LCELL( _EQ016);
_EQ016 = _LC8_A2 & !shi3
# _LC8_A2 & !shi0
# _LC6_A9 & _LC8_A2;
-- Node name is ':274'
-- Equation name is '_LC7_A9', type is buried
_LC7_A9 = LCELL( _EQ017);
_EQ017 = _LC2_A1 & !_LC2_A9 & shi2
# _LC2_A1 & _LC2_A9 & !shi2
# !_LC8_A2 & shi2;
-- Node name is ':280'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ018);
_EQ018 = _LC2_A1 & !shi0 & shi1
# _LC2_A1 & shi0 & !shi1
# !_LC8_A2 & shi1;
-- Node name is '~392~1'
-- Equation name is '~392~1', location is LC3_A9, type is buried.
-- synthesized logic cell
_LC3_A9 = LCELL( _EQ019);
_EQ019 = !_LC8_A2 & !stop;
-- Node name is ':392'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ020);
_EQ020 = ge3 & _LC3_A9 & !_LC5_A2
# !ge2 & ge3 & _LC3_A9
# ge2 & !ge3 & _LC3_A9 & _LC5_A2;
-- Node name is ':398'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ021);
_EQ021 = !ge1 & ge2 & _LC3_A9
# !ge0 & ge2 & _LC3_A9
# ge0 & ge1 & !ge2 & _LC3_A9;
-- Node name is ':404'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ022);
_EQ022 = !ge0 & ge1 & _LC3_A9
# ge0 & !ge1 & _LC3_A9;
-- Node name is ':429'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ023);
_EQ023 = !_LC8_A2
# !shi3
# !shi0
# _LC6_A9;
Project Information d:\mux\kechengsheji\zhengshu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,031K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -