📄 xiaosh.rpt
字号:
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\mux\kechengsheji\xiaosh.rpt
xiaosh
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\mux\kechengsheji\xiaosh.rpt
xiaosh
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 reset
Device-Specific Information: d:\mux\kechengsheji\xiaosh.rpt
xiaosh
** EQUATIONS **
able : INPUT;
clk : INPUT;
en : INPUT;
reset : INPUT;
stop : INPUT;
-- Node name is ':23' = 'baifen0'
-- Equation name is 'baifen0', location is LC4_B17, type is buried.
baifen0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !baifen0 & _LC2_B13
# baifen0 & !en
# baifen0 & stop;
-- Node name is 'baifen_00'
-- Equation name is 'baifen_00', type is output
baifen_00 = baifen0;
-- Node name is ':22' = 'baifen1'
-- Equation name is 'baifen1', location is LC7_B17, type is buried.
baifen1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = en & _LC1_B17 & !stop
# baifen1 & !en
# baifen1 & stop;
-- Node name is 'baifen_01'
-- Equation name is 'baifen_01', type is output
baifen_01 = baifen1;
-- Node name is ':21' = 'baifen2'
-- Equation name is 'baifen2', location is LC3_B17, type is buried.
baifen2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = en & _LC5_B17 & !stop
# baifen2 & !en
# baifen2 & stop;
-- Node name is 'baifen_02'
-- Equation name is 'baifen_02', type is output
baifen_02 = baifen2;
-- Node name is ':20' = 'baifen3'
-- Equation name is 'baifen3', location is LC2_B17, type is buried.
baifen3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = en & _LC8_B17 & !stop
# baifen3 & !en
# baifen3 & stop;
-- Node name is 'baifen_03'
-- Equation name is 'baifen_03', type is output
baifen_03 = baifen3;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC6_B13;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_B19, type is buried.
-- synthesized logic cell
!_LC1_B19 = _LC1_B19~NOT;
_LC1_B19~NOT = LCELL(!reset);
-- Node name is ':19' = 'shifen0'
-- Equation name is 'shifen0', location is LC1_B18, type is buried.
shifen0 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = _LC2_B13 & !shifen0
# !en & shifen0
# shifen0 & stop;
-- Node name is ':18' = 'shifen1'
-- Equation name is 'shifen1', location is LC3_B18, type is buried.
shifen1 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = en & _LC2_B18 & !stop
# !en & shifen1
# shifen1 & stop;
-- Node name is ':17' = 'shifen2'
-- Equation name is 'shifen2', location is LC8_B18, type is buried.
shifen2 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = en & _LC4_B18 & !stop
# !en & shifen2
# shifen2 & stop;
-- Node name is ':16' = 'shifen3'
-- Equation name is 'shifen3', location is LC5_B18, type is buried.
shifen3 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = en & _LC7_B18 & !stop
# !en & shifen3
# shifen3 & stop;
-- Node name is 'shifen_10'
-- Equation name is 'shifen_10', type is output
shifen_10 = shifen0;
-- Node name is 'shifen_11'
-- Equation name is 'shifen_11', type is output
shifen_11 = shifen1;
-- Node name is 'shifen_12'
-- Equation name is 'shifen_12', type is output
shifen_12 = shifen2;
-- Node name is 'shifen_13'
-- Equation name is 'shifen_13', type is output
shifen_13 = shifen3;
-- Node name is 'stop~1'
-- Equation name is 'stop~1', location is LC2_B13, type is buried.
-- synthesized logic cell
_LC2_B13 = LCELL( _EQ009);
_EQ009 = en & !_LC5_B13 & !stop
# !able & en & !stop;
-- Node name is '|LPM_ADD_SUB:297|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B17', type is buried
_LC6_B17 = LCELL( _EQ010);
_EQ010 = baifen0 & baifen1;
-- Node name is '|LPM_ADD_SUB:306|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ011);
_EQ011 = shifen0 & shifen1;
-- Node name is ':6'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, !_LC1_B19);
_EQ012 = en & _LC8_B13
# !en & _LC6_B13;
-- Node name is '~173~1'
-- Equation name is '~173~1', location is LC1_B13, type is buried.
-- synthesized logic cell
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL( _EQ013);
_EQ013 = !shifen3
# !baifen3;
-- Node name is '~173~2'
-- Equation name is '~173~2', location is LC7_B13, type is buried.
-- synthesized logic cell
!_LC7_B13 = _LC7_B13~NOT;
_LC7_B13~NOT = LCELL( _EQ014);
_EQ014 = !shifen3
# !baifen3
# baifen2
# baifen1;
-- Node name is ':173'
-- Equation name is '_LC8_B13', type is buried
!_LC8_B13 = _LC8_B13~NOT;
_LC8_B13~NOT = LCELL( _EQ015);
_EQ015 = !shifen0
# !baifen0
# !_LC2_B21
# !_LC7_B13;
-- Node name is ':355'
-- Equation name is '_LC3_B13', type is buried
!_LC3_B13 = _LC3_B13~NOT;
_LC3_B13~NOT = LCELL( _EQ016);
_EQ016 = !baifen0 & !baifen1 & !baifen2;
-- Node name is '~376~1'
-- Equation name is '~376~1', location is LC2_B21, type is buried.
-- synthesized logic cell
_LC2_B21 = LCELL( _EQ017);
_EQ017 = !shifen1 & !shifen2;
-- Node name is ':388'
-- Equation name is '_LC5_B13', type is buried
!_LC5_B13 = _LC5_B13~NOT;
_LC5_B13~NOT = LCELL( _EQ018);
_EQ018 = !_LC1_B13
# _LC2_B21 & !shifen0
# !_LC3_B13;
-- Node name is ':477'
-- Equation name is '_LC8_B17', type is buried
_LC8_B17 = LCELL( _EQ019);
_EQ019 = baifen3 & _LC4_B13 & !_LC6_B17
# !baifen2 & baifen3 & _LC4_B13
# baifen2 & !baifen3 & _LC4_B13 & _LC6_B17;
-- Node name is ':483'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = LCELL( _EQ020);
_EQ020 = !baifen1 & baifen2 & _LC4_B13
# !baifen0 & baifen2 & _LC4_B13
# baifen0 & baifen1 & !baifen2 & _LC4_B13;
-- Node name is '~489~1'
-- Equation name is '~489~1', location is LC4_B13, type is buried.
-- synthesized logic cell
_LC4_B13 = LCELL( _EQ021);
_EQ021 = able & !_LC5_B13
# !able & !_LC8_B13;
-- Node name is ':489'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = LCELL( _EQ022);
_EQ022 = !baifen0 & baifen1 & _LC4_B13
# baifen0 & !baifen1 & _LC4_B13;
-- Node name is ':501'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = LCELL( _EQ023);
_EQ023 = _LC4_B13 & !_LC6_B18 & shifen3
# _LC4_B13 & !shifen2 & shifen3
# _LC4_B13 & _LC6_B18 & shifen2 & !shifen3;
-- Node name is ':507'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ024);
_EQ024 = _LC4_B13 & !shifen1 & shifen2
# _LC4_B13 & !shifen0 & shifen2
# _LC4_B13 & shifen0 & shifen1 & !shifen2;
-- Node name is ':513'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ025);
_EQ025 = _LC4_B13 & !shifen0 & shifen1
# _LC4_B13 & shifen0 & !shifen1;
Project Information d:\mux\kechengsheji\xiaosh.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,575K
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