📄 vb48.rpt
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Device-Specific Information: f:\sss\vb48.rpt
vb48
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
bin : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC3_A2;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC1_A2;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC5_A2;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC8_A2;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC4_A2;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC2_A2;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC7_A3;
-- Node name is ':332'
-- Equation name is '_LC7_A11', type is buried
!_LC7_A11 = _LC7_A11~NOT;
_LC7_A11~NOT = LCELL( _EQ001);
_EQ001 = a3
# a1
# !a2
# a0;
-- Node name is ':368'
-- Equation name is '_LC3_A11', type is buried
!_LC3_A11 = _LC3_A11~NOT;
_LC3_A11~NOT = LCELL( _EQ002);
_EQ002 = a1
# a2
# !a0
# a3;
-- Node name is ':380'
-- Equation name is '_LC2_A11', type is buried
!_LC2_A11 = _LC2_A11~NOT;
_LC2_A11~NOT = LCELL( _EQ003);
_EQ003 = a1
# a2
# a0
# a3;
-- Node name is ':383'
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ004);
_EQ004 = a1 & !a2 & !a3
# a0 & a1 & !a3
# a0 & a2 & !a3
# !a1 & !a2 & a3
# !a0 & !a2 & !a3;
-- Node name is '~416~1'
-- Equation name is '~416~1', location is LC4_A11, type is buried.
-- synthesized logic cell
_LC4_A11 = LCELL( _EQ005);
_EQ005 = a0 & a1 & a2 & !a3
# !a1 & !a2;
-- Node name is ':448'
-- Equation name is '_LC5_A11', type is buried
_LC5_A11 = LCELL( _EQ006);
_EQ006 = a0 & a1 & !a3
# !a1 & a2 & !a3
# !a1 & !a2 & a3
# !a0 & a2 & !a3;
-- Node name is ':467'
-- Equation name is '_LC8_A11', type is buried
_LC8_A11 = LCELL( _EQ007);
_EQ007 = a0 & !a1 & a2 & !a3
# !a0 & !a1 & !a2 & a3
# !a0 & a1 & a2 & !a3;
-- Node name is ':476'
-- Equation name is '_LC6_A11', type is buried
_LC6_A11 = LCELL( _EQ008);
_EQ008 = !_LC7_A11 & _LC8_A11
# _LC2_A3;
-- Node name is ':509'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ009);
_EQ009 = !a0 & !a1 & !a2 & a3
# !a0 & a1 & !a3;
-- Node name is ':536'
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = LCELL( _EQ010);
_EQ010 = !a1 & a2 & !a3
# !a0 & a2 & !a3
# !a1 & !a2 & a3;
-- Node name is ':550'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ011);
_EQ011 = _LC1_A11 & !_LC2_A3 & !_LC3_A11;
-- Node name is '~575~1'
-- Equation name is '~575~1', location is LC2_A3, type is buried.
-- synthesized logic cell
_LC2_A3 = LCELL( _EQ012);
_EQ012 = a1 & !a2 & !a3;
-- Node name is ':615'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ013);
_EQ013 = !bin & _LC3_A3;
-- Node name is ':621'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ014);
_EQ014 = !bin & _LC4_A11
# !bin & _LC7_A11
# !bin & _LC2_A3;
-- Node name is ':627'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ015);
_EQ015 = !bin & _LC3_A11
# !bin & _LC2_A11
# !bin & _LC5_A11;
-- Node name is ':633'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = LCELL( _EQ016);
_EQ016 = !bin & !_LC3_A11 & _LC6_A11
# !bin & _LC2_A11;
-- Node name is ':639'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ017);
_EQ017 = !bin & _LC1_A3 & !_LC3_A11
# !bin & _LC2_A11;
-- Node name is ':645'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ018);
_EQ018 = !bin & _LC7_A2
# !bin & _LC2_A11;
-- Node name is '~651~1'
-- Equation name is '~651~1', location is LC6_A2, type is buried.
-- synthesized logic cell
_LC6_A2 = LCELL( _EQ019);
_EQ019 = !_LC2_A11 & !_LC3_A11;
-- Node name is ':651'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ020);
_EQ020 = !bin & _LC2_A3 & _LC6_A2
# !bin & _LC1_A11 & _LC6_A2;
Project Information f:\sss\vb48.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,332K
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