shengli1.rpt

出租车的计费系统

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Device-Specific Information:                      f:\kechengsheji\shengli1.rpt
shengli1

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        4         cp2
INPUT        3         cp1


Device-Specific Information:                      f:\kechengsheji\shengli1.rpt
shengli1

** EQUATIONS **

cp1      : INPUT;
cp2      : INPUT;

-- Node name is 'l0' 
-- Equation name is 'l0', type is output 
l0       = !_LC1_A16;

-- Node name is 'l1' 
-- Equation name is 'l1', type is output 
l1       = !_LC3_A16;

-- Node name is 'l2' 
-- Equation name is 'l2', type is output 
l2       = !_LC8_A16;

-- Node name is 'l3' 
-- Equation name is 'l3', type is output 
l3       = !_LC5_A13;

-- Node name is 'l4' 
-- Equation name is 'l4', type is output 
l4       = !_LC2_A16;

-- Node name is 'l5' 
-- Equation name is 'l5', type is output 
l5       = !_LC6_A16;

-- Node name is 'l6' 
-- Equation name is 'l6', type is output 
l6       = !_LC4_A16;

-- Node name is 'l7' 
-- Equation name is 'l7', type is output 
l7       =  _LC7_A16;

-- Node name is 'y0' 
-- Equation name is 'y0', type is output 
y0       =  _LC2_C12;

-- Node name is 'y1' 
-- Equation name is 'y1', type is output 
y1       =  _LC5_C12;

-- Node name is 'y2' 
-- Equation name is 'y2', type is output 
y2       =  _LC1_C12;

-- Node name is 'y3' 
-- Equation name is 'y3', type is output 
y3       =  _LC6_C12;

-- Node name is 'y4' 
-- Equation name is 'y4', type is output 
y4       =  _LC4_C12;

-- Node name is 'y5' 
-- Equation name is 'y5', type is output 
y5       =  _LC3_C12;

-- Node name is 'y6' 
-- Equation name is 'y6', type is output 
y6       =  _LC8_C12;

-- Node name is '|LX8:22|:306' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ001);
  _EQ001 = !_LC5_A16
         # !_LC3_A13
         # !_LC4_A13;

-- Node name is '|M8:18|:8' = '|M8:18|qo0' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = DFFE(!_LC4_A13, GLOBAL( cp1),  VCC,  VCC,  VCC);

-- Node name is '|M8:18|:7' = '|M8:18|qo1' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ002, GLOBAL( cp1),  VCC,  VCC,  VCC);
  _EQ002 = !_LC3_A13 &  _LC4_A13
         #  _LC3_A13 & !_LC4_A13;

-- Node name is '|M8:18|:6' = '|M8:18|qo2' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = DFFE( _EQ003, GLOBAL( cp1),  VCC,  VCC,  VCC);
  _EQ003 = !_LC4_A13 &  _LC5_A16
         # !_LC3_A13 &  _LC5_A16
         #  _LC3_A13 &  _LC4_A13 & !_LC5_A16;

-- Node name is '|SELECT48:26|:107' 
-- Equation name is '_LC1_A16', type is buried 
_LC1_A16 = LCELL( _EQ004);
  _EQ004 = !_LC3_A13 & !_LC4_A13 & !_LC5_A16;

-- Node name is '|SELECT48:26|:114' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = LCELL( _EQ005);
  _EQ005 = !_LC3_A13 &  _LC4_A13 & !_LC5_A16;

-- Node name is '|SELECT48:26|:121' 
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = LCELL( _EQ006);
  _EQ006 =  _LC3_A13 & !_LC4_A13 & !_LC5_A16;

-- Node name is '|SELECT48:26|:128' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ007);
  _EQ007 =  _LC3_A13 &  _LC4_A13 & !_LC5_A16;

-- Node name is '|SELECT48:26|:135' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ008);
  _EQ008 = !_LC3_A13 & !_LC4_A13 &  _LC5_A16;

-- Node name is '|SELECT48:26|:142' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ009);
  _EQ009 = !_LC3_A13 &  _LC4_A13 &  _LC5_A16;

-- Node name is '|SELECT48:26|:149' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = LCELL( _EQ010);
  _EQ010 =  _LC3_A13 & !_LC4_A13 &  _LC5_A16;

-- Node name is '|SELECT48:26|:339' 
-- Equation name is '_LC2_C8', type is buried 
_LC2_C8  = LCELL( _EQ011);
  _EQ011 = !_LC1_C6 &  _LC2_C8
         #  _LC1_C6 &  _LC7_C8;

-- Node name is '|SELECT48:26|~366~1' 
-- Equation name is '_LC1_C6', type is buried 
-- synthesized logic cell 
_LC1_C6  = LCELL( VCC);

-- Node name is '|SELECT48:26|:366' 
-- Equation name is '_LC3_C8', type is buried 
_LC3_C8  = LCELL( _EQ012);
  _EQ012 = !_LC1_C6 &  _LC3_C8
         #  _LC1_C6 &  _LC6_C8;

-- Node name is '|SELECT48:26|:393' 
-- Equation name is '_LC4_C8', type is buried 
_LC4_C8  = LCELL( _EQ013);
  _EQ013 = !_LC1_C6 &  _LC4_C8
         #  _LC1_C6 &  _LC5_C8;

-- Node name is '|SELECT48:26|:420' 
-- Equation name is '_LC1_C8', type is buried 
_LC1_C8  = LCELL( _EQ014);
  _EQ014 = !_LC1_C6 &  _LC1_C8
         #  _LC1_C6 &  _LC8_C8;

-- Node name is '|TEN:15|:10' = '|TEN:15|qo0' 
-- Equation name is '_LC8_C8', type is buried 
_LC8_C8  = DFFE( _EQ015, GLOBAL( cp2),  VCC,  VCC,  VCC);
  _EQ015 = !_LC5_C8 & !_LC6_C8 & !_LC8_C8
         # !_LC7_C8 & !_LC8_C8;

-- Node name is '|TEN:15|:9' = '|TEN:15|qo1' 
-- Equation name is '_LC5_C8', type is buried 
_LC5_C8  = DFFE( _EQ016, GLOBAL( cp2),  VCC,  VCC,  VCC);
  _EQ016 = !_LC5_C8 & !_LC7_C8 &  _LC8_C8
         #  _LC5_C8 & !_LC7_C8 & !_LC8_C8;

-- Node name is '|TEN:15|:8' = '|TEN:15|qo2' 
-- Equation name is '_LC6_C8', type is buried 
_LC6_C8  = DFFE( _EQ017, GLOBAL( cp2),  VCC,  VCC,  VCC);
  _EQ017 =  _LC6_C8 & !_LC7_C8 & !_LC8_C8
         # !_LC5_C8 &  _LC6_C8 & !_LC7_C8
         #  _LC5_C8 & !_LC6_C8 & !_LC7_C8 &  _LC8_C8;

-- Node name is '|TEN:15|:7' = '|TEN:15|qo3' 
-- Equation name is '_LC7_C8', type is buried 
_LC7_C8  = DFFE( _EQ018, GLOBAL( cp2),  VCC,  VCC,  VCC);
  _EQ018 =  _LC5_C8 &  _LC6_C8 & !_LC7_C8 &  _LC8_C8
         # !_LC5_C8 & !_LC6_C8 &  _LC7_C8 & !_LC8_C8;

-- Node name is '|VB48:25|:383' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = LCELL( _EQ019);
  _EQ019 =  _LC1_C8 & !_LC2_C8 &  _LC3_C8
         # !_LC2_C8 & !_LC3_C8 &  _LC4_C8
         #  _LC1_C8 & !_LC2_C8 &  _LC4_C8
         #  _LC2_C8 & !_LC3_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC2_C8 & !_LC3_C8;

-- Node name is '|VB48:25|:416' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = LCELL( _EQ020);
  _EQ020 = !_LC1_C8 & !_LC2_C8 & !_LC4_C8
         # !_LC3_C8 & !_LC4_C8
         #  _LC1_C8 & !_LC2_C8 &  _LC4_C8
         # !_LC2_C8 & !_LC3_C8;

-- Node name is '|VB48:25|:449' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ021);
  _EQ021 =  _LC1_C8 & !_LC2_C8
         # !_LC2_C8 & !_LC4_C8
         # !_LC3_C8 & !_LC4_C8
         # !_LC2_C8 &  _LC3_C8;

-- Node name is '|VB48:25|:482' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = LCELL( _EQ022);
  _EQ022 = !_LC1_C8 & !_LC2_C8 & !_LC3_C8
         # !_LC2_C8 & !_LC3_C8 &  _LC4_C8
         #  _LC1_C8 & !_LC2_C8 &  _LC3_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC3_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC2_C8 &  _LC4_C8;

-- Node name is '|VB48:25|:515' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = LCELL( _EQ023);
  _EQ023 = !_LC1_C8 & !_LC2_C8 & !_LC3_C8
         # !_LC1_C8 & !_LC3_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC2_C8 &  _LC4_C8;

-- Node name is '|VB48:25|:548' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = LCELL( _EQ024);
  _EQ024 = !_LC1_C8 & !_LC2_C8 &  _LC3_C8
         # !_LC2_C8 &  _LC3_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC2_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC3_C8 & !_LC4_C8
         #  _LC2_C8 & !_LC3_C8 & !_LC4_C8;

-- Node name is '|VB48:25|:583' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = LCELL( _EQ025);
  _EQ025 = !_LC2_C8 & !_LC3_C8 &  _LC4_C8
         # !_LC1_C8 & !_LC2_C8 &  _LC4_C8
         # !_LC2_C8 &  _LC3_C8 & !_LC4_C8
         # !_LC1_C8 & !_LC2_C8 &  _LC3_C8
         #  _LC2_C8 & !_LC3_C8 & !_LC4_C8;



Project Information                               f:\kechengsheji\shengli1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,886K