📄 bufu1.rpt
字号:
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\mux\kechengsheji\bufu1.rpt
bufu1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\mux\kechengsheji\bufu1.rpt
bufu1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 reset
Device-Specific Information: d:\mux\kechengsheji\bufu1.rpt
bufu1
** EQUATIONS **
clk : INPUT;
reset : INPUT;
stop : INPUT;
-- Node name is ':13' = 'bai0'
-- Equation name is 'bai0', location is LC1_B2, type is buried.
bai0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = bai0 & !_LC2_B2
# !bai0 & _LC2_B2 & !stop
# bai0 & stop;
-- Node name is ':12' = 'bai1'
-- Equation name is 'bai1', location is LC3_B12, type is buried.
bai1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = _LC2_B12 & !stop
# bai1 & !_LC2_B2
# bai1 & stop;
-- Node name is ':11' = 'bai2'
-- Equation name is 'bai2', location is LC6_B12, type is buried.
bai2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = _LC5_B12 & !stop
# bai2 & !_LC2_B2
# bai2 & stop;
-- Node name is ':10' = 'bai3'
-- Equation name is 'bai3', location is LC8_B12, type is buried.
bai3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = _LC7_B12 & !stop
# bai3 & !_LC2_B2
# bai3 & stop;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC2_B4;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_B4, type is buried.
-- synthesized logic cell
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL(!reset);
-- Node name is ':9' = 'shi0'
-- Equation name is 'shi0', location is LC3_B2, type is buried.
shi0 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !shi0 & !stop
# shi0 & stop;
-- Node name is ':8' = 'shi1'
-- Equation name is 'shi1', location is LC4_B2, type is buried.
shi1 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = !_LC2_B2 & shi0 & !shi1 & !stop
# !_LC2_B2 & !shi0 & shi1
# shi1 & stop;
-- Node name is ':7' = 'shi2'
-- Equation name is 'shi2', location is LC6_B2, type is buried.
shi2 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC2_B2 & !_LC5_B2 & shi2
# !_LC2_B2 & _LC5_B2 & !shi2 & !stop
# shi2 & stop;
-- Node name is ':6' = 'shi3'
-- Equation name is 'shi3', location is LC8_B2, type is buried.
shi3 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = !_LC2_B2 & !_LC7_B2 & shi3
# !_LC2_B2 & _LC7_B2 & !shi3 & !stop
# shi3 & stop;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ009);
_EQ009 = bai0 & bai1;
-- Node name is '|LPM_ADD_SUB:191|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ010);
_EQ010 = shi0 & shi1;
-- Node name is '|LPM_ADD_SUB:191|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = LCELL( _EQ011);
_EQ011 = shi0 & shi1 & shi2;
-- Node name is ':4'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, !_LC1_B4);
_EQ012 = _LC1_B12 & _LC2_B2;
-- Node name is ':89'
-- Equation name is '_LC2_B2', type is buried
!_LC2_B2 = _LC2_B2~NOT;
_LC2_B2~NOT = LCELL( _EQ013);
_EQ013 = !shi0
# shi1
# shi2
# !shi3;
-- Node name is ':107'
-- Equation name is '_LC1_B12', type is buried
!_LC1_B12 = _LC1_B12~NOT;
_LC1_B12~NOT = LCELL( _EQ014);
_EQ014 = !bai0
# bai1
# bai2
# !bai3;
-- Node name is '~234~1'
-- Equation name is '~234~1', location is LC8_B4, type is buried.
-- synthesized logic cell
_LC8_B4 = LCELL( _EQ015);
_EQ015 = !_LC1_B12 & _LC2_B2;
-- Node name is ':234'
-- Equation name is '_LC7_B12', type is buried
_LC7_B12 = LCELL( _EQ016);
_EQ016 = !bai2 & bai3 & _LC8_B4
# bai3 & !_LC4_B12 & _LC8_B4
# bai2 & !bai3 & _LC4_B12 & _LC8_B4;
-- Node name is ':240'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ017);
_EQ017 = bai2 & !_LC1_B12 & _LC2_B2 & !_LC4_B12
# !bai2 & !_LC1_B12 & _LC2_B2 & _LC4_B12;
-- Node name is ':246'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ018);
_EQ018 = bai0 & !bai1 & !_LC1_B12 & _LC2_B2
# !bai0 & bai1 & !_LC1_B12 & _LC2_B2;
Project Information d:\mux\kechengsheji\bufu1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,847K
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