u盘电路设计.drc

USB_FLASH 大容量U盘电路设计,很有参考意义

Protel Design System Design Rule Check
PCB File : \Program Files\Altium2004\Examples\U盘电路设计\U盘电路设计.PcbDoc
Date     : 2008-9-22
Time     : 17:48:52

Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.3mm) (InNet('VCC'))
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
   Violation         Net VCC   is broken into 3 sub-nets. Routed To 92.59%
     Subnet : P1-1     U4-27    U4-32    R16-1    R2-2     R1-2     U4-1     C19-1    R7-2     R8-2     
              R10-2    R9-2     U4-4     C8-2     C9-1     U4-43    C7-2     C6-2     U2-5     C12-1    U4-39    
              C5-2     C11-2    C13-2    C4-2     C3-2     
     Subnet : U1-12    
     Subnet : U1-36    
Rule Violations :1

Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.2mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
   Violation         Pad Free-0(37.846mm,119.38mm)  Multi-Layer  Actual Hole Size = 3mm
   Violation         Pad Free-1(121.92mm,119.634mm)  Multi-Layer  Actual Hole Size = 3mm
   Violation         Pad Free-2(121.92mm,91.694mm)  Multi-Layer  Actual Hole Size = 3mm
   Violation         Pad Free-3(38.481mm,91.313mm)  Multi-Layer  Actual Hole Size = 3mm
Rule Violations :4


Violations Detected : 5
Time Elapsed        : 00:00:01