crc_tb.vhd

VHDL cyclic redundancy check generator und receiver

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-- Description : This is a testbench for the design crc: x^4 + x^3 + x^0 = 11001 
--               for testpurposes only
-- References  : 
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-- Author      : Kurt Illmayer (IL) 
-- Department  : Bulme Graz Goesting 
-- Created     : 
-- Last update : 2005/06/29
-- Language    : vhdl '87 
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-- Revisions   : 
-- Date         Version   Author   Description 
-- 
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity crc_tb is
-- empty
end crc_tb;

architecture test of crc_tb is
	-- system clock
 signal clock_i           : std_ulogic;
        -- active low reset
 signal reset_ni          : std_ulogic;
	-- activation
 signal enable_i          : std_ulogic;
        -- input signal
 signal data_i            : std_ulogic_vector(7 downto 0);
        -- output signal
 signal data_crc_o        : std_ulogic_vector(11 downto 0);
 
 component crc
 port(  -- System clock
        clock_i           : in  std_ulogic;
        -- active low reset
        reset_ni          : in  std_ulogic;
    	-- activation
        enable_i          : IN  std_ulogic;
	-- input data
        data_i            : in  std_ulogic_vector(7 downto 0);
        -- output data with 4 bit remainder
        data_crc_o        : out std_ulogic_vector(11 downto 0));
 end component;
  
begin

 UUT: crc port map (clock_i          => clock_i,
  	            reset_ni         => reset_ni,
		    enable_i         => enable_i,
                    data_i           => data_i,
		    data_crc_o       => data_crc_o);
 
 reset_ni <= '0' after  0 ns,
	     '1' after 40 ns;

 data_i   <= "10100011" after     0 ns,
	     "01110001" after  9000 ns,
	     "00110011" after 18000 ns,
	     "11111111" after 27000 ns;

 enable_i <= '1' after    10 ns,
             '0' after 40500 ns;
 
 clock_p: process

 begin  
   
   clock_i <='1';

   wait for 500 ns;

   clock_i <='0';

   wait for 500 ns;
   
 end process clock_p;
 
end test;