crc_rtl.vhd

VHDL cyclic redundancy check generator und receiver

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-- Description : This is a crc design unit for testpurposes only
--               crc-4: x^4 + x^3 + x^0 := 11001
-- References  : 
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-- Author      : Kurt Illmayer (IL) 
-- Department  : Bulme Graz Goesting 
-- Created     : 
-- Last update : 2005/06/29
-- Language    : vhdl '87 
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-- Revisions   : 
-- Date         Version   Author   Description 
-- 
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity crc is
 port(-- System clock
      clock_i        : in  std_ulogic;
      -- active low reset
      reset_ni       : in  std_ulogic;
      -- enable_i input signal 
      enable_i       : in  std_ulogic;
      -- input data (8 bit data)
      data_i         : in  std_ulogic_vector(7 downto 0); 
      -- output data with crc checksum
      data_crc_o     : out std_ulogic_vector(11 downto 0));
end crc;

architecture rtl of crc is

 signal	data_calc     : std_ulogic_vector(5 downto 0);
 
 signal	data_crc      : std_ulogic_vector(11 downto 0);
          -- x^4 + x^3 + x^0 := 11001
 constant crc_polynom : std_ulogic_vector(4 downto 0):="11001";

 -- statemachine definitions 
 type states is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9);
 -- state signal 
 signal state : states; 
 
begin

  crc_p: process (clock_i, reset_ni)
	
  begin

    if (reset_ni = '0') then

      data_crc(11 downto 0)   <= (others=>'0');      

      data_calc(5 downto 0)   <= (others=>'0');

      data_crc_o(11 downto 0) <= (others=>'0');
      
      state                   <= S0;
      
    elsif (clock_i'event and clock_i ='1') then

       case state is

	 when  S0 => if(enable_i = '1') then
			 
	                data_calc(5 downto 1) <= data_i(7 downto 3);

	                data_crc(11 downto 4) <= data_i(7 downto 0);

 		        state                 <= S1;
			
                     else

 		        state                 <= S0;
			
		     end if;
			
         when S1 =>  if (data_calc(5) = '1') then

			data_calc(5 downto 0) <= (data_crc(11 downto 7) xor crc_polynom(4 downto 0)) & data_crc(6);
			
 		        state                 <= S2;

		     else
			 
			data_calc(0)          <= data_crc(6);
			
 		        state                 <= S2;
			
                     end if;
			
	 when S2 =>  if (data_calc(4) = '1') then

	         	data_calc(5 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0)) & data_crc(5);
			
 		        state                 <= S3;
			
                     else

	    	        data_calc(5 downto 0) <= data_calc(4 downto 0) & data_crc(5);

 		        state                 <= S3;
			
                     end if;

	 when S3 =>  if (data_calc(4) = '1') then

	         	data_calc(5 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0)) & data_crc(4);
			
 		        state                 <= S4;
			
                     else

	    	        data_calc(5 downto 0) <= data_calc(4 downto 0) & data_crc(4);

 		        state                 <= S4;
			
                     end if;

	 when S4 =>  if (data_calc(4) = '1') then

	         	data_calc(5 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0)) & data_crc(3);
			
 		        state                 <= S5;
			
                     else

	    	        data_calc(5 downto 0) <= data_calc(4 downto 0) & data_crc(3);

 		        state                 <= S5;
			
                     end if;

	 when S5 =>  if (data_calc(4) = '1') then

	         	data_calc(5 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0)) & data_crc(2);
			
 		        state                 <= S6;
			
                     else

	    	        data_calc(5 downto 0) <= data_calc(4 downto 0) & data_crc(2);

 		        state                 <= S6;
			
                     end if;

	 when S6 =>  if (data_calc(4) = '1') then

	         	data_calc(5 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0)) & data_crc(1);
			
 		        state                 <= S7;
			
                     else

	    	        data_calc(5 downto 0) <= data_calc(4 downto 0) & data_crc(1);

 		        state                 <= S7;
			
                     end if;

	 when S7 =>  if (data_calc(4) = '1') then

	         	data_calc(5 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0)) & data_crc(0);
			
 		        state                 <= S8;
			
                     else

	    	        data_calc(5 downto 0) <= data_calc(4 downto 0) & data_crc(0);

 		        state                 <= S8;
			
                     end if;		     

	 when S8 =>  if (data_calc(4) = '1') then

	         	data_calc(4 downto 0) <= (data_calc(4 downto 0) xor crc_polynom(4 downto 0));

 		        state                 <= S9;
                 
		     else

   	                state                 <= S9;					  
					  
		     end if;	
		     
	 when S9 =>  -- data_calc(3 downto 0)  	-- rest bzw. residue bzw. remainder			   
                     data_crc_o(11 downto 0)  <= data_crc(11 downto 4) & data_calc(3 downto 0);  

 		     state                    <= S0;
		     
	 when others => null;

       end case;

    end if;
       
  end process crc_p;

end rtl;