risc_spm.v

来自「这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现」· Verilog 代码 · 共 35 行

module rsic(clk, rst);
  parameter word_size = 16;//数据位
  parameter address_size = 8;//地址位
  parameter Sel1_size = 3;
  parameter Sel2_size = 2;
  wire [Sel1_size-1: 0] Sel_Bus_1_Mux;
  wire [Sel2_size-1: 0] Sel_Bus_2_Mux;

  input clk, rst;

  // Data Nets
  wire zero, Carrier_flag;
  wire [word_size-1: 0] instruction, Bus_1, mem_word;
  wire [address_size-1 : 0] address; 
   
  // Control Nets
  wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR;   
  wire Load_Add_R, Load_Reg_Y, Load_Reg_Z, Load_Carrier;
  wire write;
 
  Processing_Unit M0_Processor (instruction, zero, Carrier_flag, address, Bus_1, mem_word, Load_R0, Load_R1,
    Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Load_IR, Load_Add_R, Load_Reg_Y,
    Load_Reg_Z, Load_Carrier, Sel_Bus_2_Mux, clk, rst);

  Control_Unit M1_Controller (Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, 
    Sel_Bus_1_Mux, Sel_Bus_2_Mux , Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, Load_Carrier,
    write, instruction, zero, Carrier_flag, clk, rst);//调用控制模块

  Memory_Unit M2_SRAM (
    .data_out(mem_word), 
    .data_in(Bus_1), 
    .address(address), 
    .clk(clk),
    .write(write) );//调用寄存模块
endmodule