rsic.hif

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

Version 5.1 Build 176 10/26/2005 SJ Full Version
10
728
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
rsic
# storage
db|rsic.(0).cnf
db|rsic.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RISC_SPM.v
2d27b39b9d90e63635d4f2a11757e4b
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
address_size
8
PARAMETER_DEC
DEF
Sel1_size
3
PARAMETER_DEC
DEF
Sel2_size
2
PARAMETER_DEC
DEF
}
# hierarchies {
|
}
# end
# entity
Processing_Unit
# storage
db|rsic.(1).cnf
db|rsic.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
address_size
8
PARAMETER_DEC
DEF
op_size
4
PARAMETER_DEC
DEF
Sel1_size
3
PARAMETER_DEC
DEF
Sel2_size
2
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor
}
# end
# entity
Register_Unit
# storage
db|rsic.(2).cnf
db|rsic.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Register_Unit:R0
Processing_Unit:M0_Processor|Register_Unit:R1
Processing_Unit:M0_Processor|Register_Unit:R2
Processing_Unit:M0_Processor|Register_Unit:R3
Processing_Unit:M0_Processor|Register_Unit:Reg_Y
}
# end
# entity
D_flop
# storage
db|rsic.(3).cnf
db|rsic.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Processing_Unit:M0_Processor|D_flop:Reg_Z
Processing_Unit:M0_Processor|D_flop:Reg_C
}
# end
# entity
Address_Register
# storage
db|rsic.(4).cnf
db|rsic.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
address_size
8
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Address_Register:Add_R
}
# end
# entity
Instruction_Register
# storage
db|rsic.(5).cnf
db|rsic.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Instruction_Register:IR
}
# end
# entity
Program_Counter
# storage
db|rsic.(6).cnf
db|rsic.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
address_size
8
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Program_Counter:PC
}
# end
# entity
Multiplexer_6ch
# storage
db|rsic.(7).cnf
db|rsic.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Multiplexer_6ch:Mux_1
}
# end
# entity
Multiplexer_3ch
# storage
db|rsic.(8).cnf
db|rsic.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Multiplexer_3ch:Mux_2
}
# end
# entity
Alu_RISC
# storage
db|rsic.(9).cnf
db|rsic.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Processing_Unit.v
62a42618355cc553f17ba195c36bf781
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
op_size
4
PARAMETER_DEC
DEF
NOP
0000
PARAMETER_BIN
DEF
ADD
0001
PARAMETER_BIN
DEF
SUB
0010
PARAMETER_BIN
DEF
DCC
0100
PARAMETER_BIN
DEF
RD
0101
PARAMETER_BIN
DEF
WR
0110
PARAMETER_BIN
DEF
ID_WR
0011
PARAMETER_BIN
DEF
BR
0111
PARAMETER_BIN
DEF
BRZ
1000
PARAMETER_BIN
DEF
ADDC
1001
PARAMETER_BIN
DEF
ID_RD
1010
PARAMETER_BIN
DEF
shift
1011
PARAMETER_BIN
DEF
ACC
1100
PARAMETER_BIN
DEF
BRC
1101
PARAMETER_BIN
DEF
compare
1110
PARAMETER_BIN
DEF
LD
1111
PARAMETER_BIN
DEF
}
# hierarchies {
Processing_Unit:M0_Processor|Alu_RISC:ALU
}
# end
# entity
Control_Unit
# storage
db|rsic.(10).cnf
db|rsic.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Control_Unit.v
55adae0c2bcfc2458fb6e2f4bca6bbf
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
op_size
4
PARAMETER_DEC
DEF
state_size
4
PARAMETER_DEC
DEF
address_size
8
PARAMETER_DEC
DEF
src_size
2
PARAMETER_DEC
DEF
dest_size
2
PARAMETER_DEC
DEF
Sel1_size
3
PARAMETER_DEC
DEF
Sel2_size
2
PARAMETER_DEC
DEF
S_idle
0
PARAMETER_DEC
DEF
S_fet1
1
PARAMETER_DEC
DEF
S_fet2
2
PARAMETER_DEC
DEF
S_dec
3
PARAMETER_DEC
DEF
S_ex1
4
PARAMETER_DEC
DEF
S_rd1
5
PARAMETER_DEC
DEF
S_wr1
6
PARAMETER_DEC
DEF
S_br1
7
PARAMETER_DEC
DEF
S_halt
8
PARAMETER_DEC
DEF
S_brz
11
PARAMETER_DEC
DEF
S_lw
9
PARAMETER_DEC
DEF
S_rw
10
PARAMETER_DEC
DEF
S_cmp
12
PARAMETER_DEC
DEF
NOP
0
PARAMETER_DEC
DEF
ADD
1
PARAMETER_DEC
DEF
SUB
2
PARAMETER_DEC
DEF
ID_WR
3
PARAMETER_DEC
DEF
DCC
4
PARAMETER_DEC
DEF
RD
5
PARAMETER_DEC
DEF
WR
6
PARAMETER_DEC
DEF
BR
7
PARAMETER_DEC
DEF
BRZ
8
PARAMETER_DEC
DEF
ADDC
9
PARAMETER_DEC
DEF
ID_RD
10
PARAMETER_DEC
DEF
shift
11
PARAMETER_DEC
DEF
ACC
12
PARAMETER_DEC
DEF
BRC
13
PARAMETER_DEC
DEF
compare
14
PARAMETER_DEC
DEF
LD
15
PARAMETER_DEC
DEF
R0
0
PARAMETER_DEC
DEF
R1
1
PARAMETER_DEC
DEF
R2
2
PARAMETER_DEC
DEF
R3
3
PARAMETER_DEC
DEF
}
# hierarchies {
Control_Unit:M1_Controller
}
# end
# entity
Memory_Unit
# storage
db|rsic.(11).cnf
db|rsic.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Memory_Unit.v
434352a7682a198f8d2aa76626229725
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
word_size
16
PARAMETER_DEC
DEF
address_size
8
PARAMETER_DEC
DEF
memory_size
256
PARAMETER_DEC
DEF
}
# hierarchies {
Memory_Unit:M2_SRAM
}
# end
# entity
altsyncram
# storage
db|rsic.(12).cnf
db|rsic.(12).cnf
# case_insensitive
# source_file
c:|altera|quartus51|libraries|megafunctions|altsyncram.tdf
2e50408acd947bab10aa53249c64526
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
16
PARAMETER_UNKNOWN
USR
WIDTHAD_B
8
PARAMETER_UNKNOWN
USR
NUMWORDS_B
256
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_1n81
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|quartus51|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|quartus51|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
c:|altera|quartus51|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
c:|altera|quartus51|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|quartus51|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|quartus51|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
c:|altera|quartus51|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_1n81
# storage
db|rsic.(13).cnf
db|rsic.(13).cnf
# case_insensitive
# source_file
db|altsyncram_1n81.tdf
349c6b059cc5d2635d255265fbc60fc
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# end
# entity
altsyncram_uq91
# storage
db|rsic.(14).cnf
db|rsic.(14).cnf
# case_insensitive
# source_file
db|altsyncram_uq91.tdf
f8f61cb0f2731c287d32a619f7cffa
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
none
0
}
# end
# complete