rsic.map.qmsg

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(299) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(299): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 299 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "src Control_Unit.v(306) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(306): variable \"src\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 306 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(307) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(307): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 307 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(308) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(308): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 308 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(309) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(309): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 309 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(310) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(310): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 310 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(319) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(319): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 319 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(320) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(320): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 320 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(321) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(321): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 321 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(322) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(322): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 322 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(323) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(323): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 323 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Memory_Unit Memory_Unit:M2_SRAM " "Info: Elaborating entity \"Memory_Unit\" for hierarchy \"Memory_Unit:M2_SRAM\"" {  } { { "RISC_SPM.v" "M2_SRAM" { Text "E:/rsic/RISC_SPM.v" 29 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[14\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[14\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[13\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[13\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[12\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[12\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[11\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[11\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[10\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[10\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[9\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[9\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[8\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[8\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[15\] data_in GND " "Warning: Reduced register \"Processing_Unit:M0_Processor\|Program_Counter:PC\|count\[15\]\" with stuck data_in port to stuck value GND" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "Memory_Unit:M2_SRAM\|memory~0 " "Warning: Created node \"Memory_Unit:M2_SRAM\|memory~0\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." {  } { { "Memory_Unit.v" "memory~0" { Text "E:/rsic/Memory_Unit.v" 9 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|rsic\|Control_Unit:M1_Controller\|state 13 " "Info: State machine \"\|rsic\|Control_Unit:M1_Controller\|state\" contains 13 states" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|rsic\|Control_Unit:M1_Controller\|state " "Info: Selected Auto state machine encoding method for state machine \"\|rsic\|Control_Unit:M1_Controller\|state\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|rsic\|Control_Unit:M1_Controller\|state " "Info: Encoding result for state machine \"\|rsic\|Control_Unit:M1_Controller\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "13 " "Info: Completed encoding using 13 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_fet1 " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_fet1\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_fet2 " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_fet2\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_dec " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_dec\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_ex1 " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_ex1\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_cmp " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_cmp\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_rd1 " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_rd1\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_wr1 " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_wr1\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_lw " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_lw\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_rw " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_rw\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_br1 " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_br1\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_brz " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_brz\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_halt " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_halt\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control_Unit:M1_Controller\|state.S_idle " "Info: Encoded state bit \"Control_Unit:M1_Controller\|state.S_idle\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_idle 0000000000000 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_idle\" uses code string \"0000000000000\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_halt 0000000000011 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_halt\" uses code string \"0000000000011\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_brz 0000000000101 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_brz\" uses code string \"0000000000101\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_br1 0000000001001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_br1\" uses code string \"0000000001001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_rw 0000000010001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_rw\" uses code string \"0000000010001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_lw 0000000100001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_lw\" uses code string \"0000000100001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_wr1 0000001000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_wr1\" uses code string \"0000001000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_rd1 0000010000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_rd1\" uses code string \"0000010000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_cmp 0000100000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_cmp\" uses code string \"0000100000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_ex1 0001000000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_ex1\" uses code string \"0001000000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_dec 0010000000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_dec\" uses code string \"0010000000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_fet2 0100000000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_fet2\" uses code string \"0100000000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rsic\|Control_Unit:M1_Controller\|state.S_fet1 1000000000001 " "Info: State \"\|rsic\|Control_Unit:M1_Controller\|state.S_fet1\" uses code string \"1000000000001\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 36 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_T