rsic.map.qmsg

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(208) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(208): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 208 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(209) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(209): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 209 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(210) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(210): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 210 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(211) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(211): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 211 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(212) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(212): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 212 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(217) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(217): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 217 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Carrier_flag Control_Unit.v(219) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(219): variable \"Carrier_flag\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 219 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(240) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(240): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 240 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(241) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(241): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 241 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(242) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(242): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 242 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(243) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(243): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 243 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(244) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(244): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 244 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(252) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(252): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 252 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(253) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(253): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 253 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(254) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(254): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 254 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(255) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(255): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 255 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(256) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(256): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 256 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "src Control_Unit.v(264) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(264): variable \"src\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 264 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(265) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(265): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 265 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(266) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(266): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 266 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(267) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(267): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 267 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(268) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(268): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 268 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(295) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(295): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 295 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(296) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(296): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 296 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(297) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(297): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 297 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(298) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(298): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 298 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}