rsic.map.qmsg

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(120) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(120): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 120 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(121) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(121): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 121 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(122) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(122): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 122 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(123) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(123): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 123 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(129) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(129): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 129 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(132) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(132): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 132 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(133) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(133): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 133 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(134) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(134): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 134 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(135) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(135): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 135 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(136) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(136): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 136 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(163) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(163): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 163 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(168) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(168): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 168 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(173) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(173): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 173 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "src Control_Unit.v(176) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(176): variable \"src\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 176 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(177) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(177): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 177 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(178) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(178): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 178 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(179) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(179): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 179 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(180) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(180): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 180 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(186) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(186): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 186 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "dest Control_Unit.v(189) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(189): variable \"dest\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 189 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(190) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(190): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 190 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(191) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(191): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 191 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(192) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(192): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 192 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(193) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(193): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 193 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(201) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(201): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 201 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(206) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(206): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 206 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}