rsic.map.qmsg

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "WR Processing_Unit.v(168) " "Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(168): object \"WR\" assigned a value but never read" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 168 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "ID_WR Processing_Unit.v(169) " "Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(169): object \"ID_WR\" assigned a value but never read" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 169 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "BR Processing_Unit.v(170) " "Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(170): object \"BR\" assigned a value but never read" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 170 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "ID_RD Processing_Unit.v(174) " "Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(174): object \"ID_RD\" assigned a value but never read" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 174 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "BRC Processing_Unit.v(177) " "Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(177): object \"BRC\" assigned a value but never read" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 177 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 Processing_Unit.v(198) " "Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(198): truncated value with size 32 to match size of target (16)" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 198 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 Processing_Unit.v(199) " "Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(199): truncated value with size 32 to match size of target (16)" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 199 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "alu_out Processing_Unit.v(190) " "Warning (10240): Verilog HDL Always Construct warning at Processing_Unit.v(190): variable \"alu_out\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"alu_out\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 190 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "carrier Processing_Unit.v(190) " "Warning (10240): Verilog HDL Always Construct warning at Processing_Unit.v(190): variable \"carrier\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"carrier\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 190 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Control_Unit Control_Unit:M1_Controller " "Info: Elaborating entity \"Control_Unit\" for hierarchy \"Control_Unit:M1_Controller\"" {  } { { "RISC_SPM.v" "M1_Controller" { Text "E:/rsic/RISC_SPM.v" 25 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "address_size Control_Unit.v(11) " "Warning (10036): Verilog HDL or VHDL warning at Control_Unit.v(11): object \"address_size\" assigned a value but never read" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 11 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "err_flag Control_Unit.v(42) " "Warning (10036): Verilog HDL or VHDL warning at Control_Unit.v(42): object \"err_flag\" assigned a value but never read" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "address Control_Unit.v(47) " "Warning (10036): Verilog HDL or VHDL warning at Control_Unit.v(47): object \"address\" assigned a value but never read" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 47 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Control_Unit.v(54) " "Warning (10273): Verilog HDL warning at Control_Unit.v(54): sign extended using \"x\" or \"z\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 54 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: sign extended using \"x\" or \"z\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 Control_Unit.v(50) " "Warning (10230): Verilog HDL assignment warning at Control_Unit.v(50): truncated value with size 32 to match size of target (3)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Control_Unit.v(58) " "Warning (10273): Verilog HDL warning at Control_Unit.v(58): sign extended using \"x\" or \"z\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 58 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: sign extended using \"x\" or \"z\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 Control_Unit.v(57) " "Warning (10230): Verilog HDL assignment warning at Control_Unit.v(57): truncated value with size 32 to match size of target (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(99) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(99): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 99 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(100) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(100): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 100 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "src Control_Unit.v(105) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(105): variable \"src\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 105 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(106) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(106): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 106 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(107) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(107): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 107 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(108) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(108): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 108 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 Control_Unit.v(109) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(109): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 109 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Control_Unit.v(114) " "Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(114): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 114 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "src Control_Unit.v(119) " "Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(119): variable \"src\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 119 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}