rsic.hier_info

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

data_e[5] => mux_out~10.DATAB
data_e[6] => mux_out~9.DATAB
data_e[7] => mux_out~8.DATAB
data_e[8] => mux_out~7.DATAB
data_e[9] => mux_out~6.DATAB
data_e[10] => mux_out~5.DATAB
data_e[11] => mux_out~4.DATAB
data_e[12] => mux_out~3.DATAB
data_e[13] => mux_out~2.DATAB
data_e[14] => mux_out~1.DATAB
data_e[15] => mux_out~0.DATAB
data_f[0] => mux_out~15.DATAA
data_f[1] => mux_out~14.DATAA
data_f[2] => mux_out~13.DATAA
data_f[3] => mux_out~12.DATAA
data_f[4] => mux_out~11.DATAA
data_f[5] => mux_out~10.DATAA
data_f[6] => mux_out~9.DATAA
data_f[7] => mux_out~8.DATAA
data_f[8] => mux_out~7.DATAA
data_f[9] => mux_out~6.DATAA
data_f[10] => mux_out~5.DATAA
data_f[11] => mux_out~4.DATAA
data_f[12] => mux_out~3.DATAA
data_f[13] => mux_out~2.DATAA
data_f[14] => mux_out~1.DATAA
data_f[15] => mux_out~0.DATAA
sel[0] => Equal~0.IN63
sel[0] => Equal~1.IN63
sel[0] => Equal~2.IN63
sel[0] => Equal~3.IN63
sel[0] => Equal~4.IN63
sel[1] => Equal~0.IN62
sel[1] => Equal~1.IN62
sel[1] => Equal~2.IN62
sel[1] => Equal~3.IN62
sel[1] => Equal~4.IN62
sel[2] => Equal~0.IN61
sel[2] => Equal~1.IN61
sel[2] => Equal~2.IN61
sel[2] => Equal~3.IN61
sel[2] => Equal~4.IN61


|rsic|Processing_Unit:M0_Processor|Multiplexer_3ch:Mux_2
mux_out[0] <= mux_out~31.DB_MAX_OUTPUT_PORT_TYPE
mux_out[1] <= mux_out~30.DB_MAX_OUTPUT_PORT_TYPE
mux_out[2] <= mux_out~29.DB_MAX_OUTPUT_PORT_TYPE
mux_out[3] <= mux_out~28.DB_MAX_OUTPUT_PORT_TYPE
mux_out[4] <= mux_out~27.DB_MAX_OUTPUT_PORT_TYPE
mux_out[5] <= mux_out~26.DB_MAX_OUTPUT_PORT_TYPE
mux_out[6] <= mux_out~25.DB_MAX_OUTPUT_PORT_TYPE
mux_out[7] <= mux_out~24.DB_MAX_OUTPUT_PORT_TYPE
mux_out[8] <= mux_out~23.DB_MAX_OUTPUT_PORT_TYPE
mux_out[9] <= mux_out~22.DB_MAX_OUTPUT_PORT_TYPE
mux_out[10] <= mux_out~21.DB_MAX_OUTPUT_PORT_TYPE
mux_out[11] <= mux_out~20.DB_MAX_OUTPUT_PORT_TYPE
mux_out[12] <= mux_out~19.DB_MAX_OUTPUT_PORT_TYPE
mux_out[13] <= mux_out~18.DB_MAX_OUTPUT_PORT_TYPE
mux_out[14] <= mux_out~17.DB_MAX_OUTPUT_PORT_TYPE
mux_out[15] <= mux_out~16.DB_MAX_OUTPUT_PORT_TYPE
data_a[0] => mux_out~31.DATAB
data_a[1] => mux_out~30.DATAB
data_a[2] => mux_out~29.DATAB
data_a[3] => mux_out~28.DATAB
data_a[4] => mux_out~27.DATAB
data_a[5] => mux_out~26.DATAB
data_a[6] => mux_out~25.DATAB
data_a[7] => mux_out~24.DATAB
data_a[8] => mux_out~23.DATAB
data_a[9] => mux_out~22.DATAB
data_a[10] => mux_out~21.DATAB
data_a[11] => mux_out~20.DATAB
data_a[12] => mux_out~19.DATAB
data_a[13] => mux_out~18.DATAB
data_a[14] => mux_out~17.DATAB
data_a[15] => mux_out~16.DATAB
data_b[0] => mux_out~15.DATAB
data_b[1] => mux_out~14.DATAB
data_b[2] => mux_out~13.DATAB
data_b[3] => mux_out~12.DATAB
data_b[4] => mux_out~11.DATAB
data_b[5] => mux_out~10.DATAB
data_b[6] => mux_out~9.DATAB
data_b[7] => mux_out~8.DATAB
data_b[8] => mux_out~7.DATAB
data_b[9] => mux_out~6.DATAB
data_b[10] => mux_out~5.DATAB
data_b[11] => mux_out~4.DATAB
data_b[12] => mux_out~3.DATAB
data_b[13] => mux_out~2.DATAB
data_b[14] => mux_out~1.DATAB
data_b[15] => mux_out~0.DATAB
data_c[0] => mux_out~15.DATAA
data_c[1] => mux_out~14.DATAA
data_c[2] => mux_out~13.DATAA
data_c[3] => mux_out~12.DATAA
data_c[4] => mux_out~11.DATAA
data_c[5] => mux_out~10.DATAA
data_c[6] => mux_out~9.DATAA
data_c[7] => mux_out~8.DATAA
data_c[8] => mux_out~7.DATAA
data_c[9] => mux_out~6.DATAA
data_c[10] => mux_out~5.DATAA
data_c[11] => mux_out~4.DATAA
data_c[12] => mux_out~3.DATAA
data_c[13] => mux_out~2.DATAA
data_c[14] => mux_out~1.DATAA
data_c[15] => mux_out~0.DATAA
sel[0] => Equal~0.IN63
sel[0] => Equal~1.IN63
sel[1] => Equal~0.IN62
sel[1] => Equal~1.IN62


|rsic|Processing_Unit:M0_Processor|Alu_RISC:ALU
alu_zero_flag <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[0] <= alu_out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[1] <= alu_out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[2] <= alu_out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[3] <= alu_out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[4] <= alu_out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[5] <= alu_out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[6] <= alu_out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[7] <= alu_out[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[8] <= alu_out[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[9] <= alu_out[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[10] <= alu_out[10]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[11] <= alu_out[11]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[12] <= alu_out[12]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[13] <= alu_out[13]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[14] <= alu_out[14]$latch.DB_MAX_OUTPUT_PORT_TYPE
alu_out[15] <= alu_out[15]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_1[0] => add~1.IN16
data_1[0] => LessThan~0.IN16
data_1[0] => Select~3.IN18
data_1[0] => Select~15.IN17
data_1[0] => add~0.IN16
data_1[1] => add~1.IN15
data_1[1] => LessThan~0.IN15
data_1[1] => Select~2.IN18
data_1[1] => Select~14.IN17
data_1[1] => add~0.IN15
data_1[2] => add~1.IN14
data_1[2] => LessThan~0.IN14
data_1[2] => Select~1.IN18
data_1[2] => Select~13.IN17
data_1[2] => add~0.IN14
data_1[3] => add~1.IN13
data_1[3] => LessThan~0.IN13
data_1[3] => Select~0.IN18
data_1[3] => Select~12.IN17
data_1[3] => add~0.IN13
data_1[4] => add~1.IN12
data_1[4] => LessThan~0.IN12
data_1[4] => Select~11.IN17
data_1[4] => add~0.IN12
data_1[5] => add~1.IN11
data_1[5] => LessThan~0.IN11
data_1[5] => Select~10.IN17
data_1[5] => add~0.IN11
data_1[6] => add~1.IN10
data_1[6] => LessThan~0.IN10
data_1[6] => Select~9.IN17
data_1[6] => add~0.IN10
data_1[7] => add~1.IN9
data_1[7] => LessThan~0.IN9
data_1[7] => Select~8.IN17
data_1[7] => add~0.IN9
data_1[8] => add~1.IN8
data_1[8] => LessThan~0.IN8
data_1[8] => Select~7.IN17
data_1[8] => add~0.IN8
data_1[9] => add~1.IN7
data_1[9] => LessThan~0.IN7
data_1[9] => Select~6.IN17
data_1[9] => add~0.IN7
data_1[10] => add~1.IN6
data_1[10] => LessThan~0.IN6
data_1[10] => Select~5.IN17
data_1[10] => add~0.IN6
data_1[11] => add~1.IN5
data_1[11] => LessThan~0.IN5
data_1[11] => Select~4.IN17
data_1[11] => add~0.IN5
data_1[12] => add~1.IN4
data_1[12] => LessThan~0.IN4
data_1[12] => Select~3.IN17
data_1[12] => add~0.IN4
data_1[13] => add~1.IN3
data_1[13] => LessThan~0.IN3
data_1[13] => Select~2.IN17
data_1[13] => add~0.IN3
data_1[14] => add~1.IN2
data_1[14] => LessThan~0.IN2
data_1[14] => Select~1.IN17
data_1[14] => add~0.IN2
data_1[15] => add~1.IN1
data_1[15] => LessThan~0.IN1
data_1[15] => Select~0.IN17
data_1[15] => add~0.IN1
data_2[0] => add~0.IN32
data_2[0] => add~1.IN32
data_2[0] => add~2.IN32
data_2[0] => add~3.IN32
data_2[0] => LessThan~0.IN32
data_2[0] => Select~15.IN19
data_2[1] => add~0.IN31
data_2[1] => add~1.IN31
data_2[1] => add~2.IN31
data_2[1] => add~3.IN31
data_2[1] => LessThan~0.IN31
data_2[1] => Select~14.IN19
data_2[2] => add~0.IN30
data_2[2] => add~1.IN30
data_2[2] => add~2.IN30
data_2[2] => add~3.IN30
data_2[2] => LessThan~0.IN30
data_2[2] => Select~13.IN19
data_2[3] => add~0.IN29
data_2[3] => add~1.IN29
data_2[3] => add~2.IN29
data_2[3] => add~3.IN29
data_2[3] => LessThan~0.IN29
data_2[3] => Select~12.IN19
data_2[4] => add~0.IN28
data_2[4] => add~1.IN28
data_2[4] => add~2.IN28
data_2[4] => add~3.IN28
data_2[4] => LessThan~0.IN28
data_2[4] => Select~11.IN19
data_2[4] => Select~15.IN18
data_2[5] => add~0.IN27
data_2[5] => add~1.IN27
data_2[5] => add~2.IN27
data_2[5] => add~3.IN27
data_2[5] => LessThan~0.IN27
data_2[5] => Select~10.IN19
data_2[5] => Select~14.IN18
data_2[6] => add~0.IN26
data_2[6] => add~1.IN26
data_2[6] => add~2.IN26
data_2[6] => add~3.IN26
data_2[6] => LessThan~0.IN26
data_2[6] => Select~9.IN19
data_2[6] => Select~13.IN18
data_2[7] => add~0.IN25
data_2[7] => add~1.IN25
data_2[7] => add~2.IN25
data_2[7] => add~3.IN25
data_2[7] => LessThan~0.IN25
data_2[7] => Select~8.IN19
data_2[7] => Select~12.IN18
data_2[8] => add~0.IN24
data_2[8] => add~1.IN24
data_2[8] => add~2.IN24
data_2[8] => add~3.IN24
data_2[8] => LessThan~0.IN24
data_2[8] => Select~7.IN19
data_2[8] => Select~11.IN18
data_2[9] => add~0.IN23
data_2[9] => add~1.IN23
data_2[9] => add~2.IN23
data_2[9] => add~3.IN23
data_2[9] => LessThan~0.IN23
data_2[9] => Select~6.IN19
data_2[9] => Select~10.IN18
data_2[10] => add~0.IN22
data_2[10] => add~1.IN22
data_2[10] => add~2.IN22
data_2[10] => add~3.IN22
data_2[10] => LessThan~0.IN22
data_2[10] => Select~5.IN19
data_2[10] => Select~9.IN18
data_2[11] => add~0.IN21
data_2[11] => add~1.IN21
data_2[11] => add~2.IN21
data_2[11] => add~3.IN21
data_2[11] => LessThan~0.IN21
data_2[11] => Select~4.IN19
data_2[11] => Select~8.IN18
data_2[12] => add~0.IN20
data_2[12] => add~1.IN20
data_2[12] => add~2.IN20
data_2[12] => add~3.IN20
data_2[12] => LessThan~0.IN20
data_2[12] => Select~3.IN19
data_2[12] => Select~7.IN18
data_2[13] => add~0.IN19
data_2[13] => add~1.IN19
data_2[13] => add~2.IN19
data_2[13] => add~3.IN19
data_2[13] => LessThan~0.IN19
data_2[13] => Select~2.IN19
data_2[13] => Select~6.IN18
data_2[14] => add~0.IN18
data_2[14] => add~1.IN18
data_2[14] => add~2.IN18
data_2[14] => add~3.IN18
data_2[14] => LessThan~0.IN18
data_2[14] => Select~1.IN19
data_2[14] => Select~5.IN18
data_2[15] => add~0.IN17
data_2[15] => add~1.IN17
data_2[15] => add~2.IN17
data_2[15] => add~3.IN17
data_2[15] => LessThan~0.IN17
data_2[15] => Select~0.IN19
data_2[15] => Select~4.IN18
sel[0] => Decoder~0.IN3
sel[1] => Decoder~0.IN2
sel[2] => Decoder~0.IN1
sel[3] => Decoder~0.IN0


|rsic|Control_Unit:M1_Controller
Load_R0 <= Select~9.DB_MAX_OUTPUT_PORT_TYPE
Load_R1 <= Select~10.DB_MAX_OUTPUT_PORT_TYPE
Load_R2 <= Select~11.DB_MAX_OUTPUT_PORT_TYPE
Load_R3 <= Select~12.DB_MAX_OUTPUT_PORT_TYPE
Load_PC <= state.S_br1.DB_MAX_OUTPUT_PORT_TYPE
Inc_PC <= state.S_fet2.DB_MAX_OUTPUT_PORT_TYPE
Sel_Bus_1_Mux[0] <= Sel_Bus_1_Mux~9.DB_MAX_OUTPUT_PORT_TYPE
Sel_Bus_1_Mux[1] <= Sel_Bus_1_Mux~8.DB_MAX_OUTPUT_PORT_TYPE
Sel_Bus_1_Mux[2] <= Sel_Bus_1_Mux~7.DB_MAX_OUTPUT_PORT_TYPE
Sel_Bus_2_Mux[0] <= Sel_Bus_2_Mux~1.DB_MAX_OUTPUT_PORT_TYPE
Sel_Bus_2_Mux[1] <= Sel_Bus_2_Mux~0.DB_MAX_OUTPUT_PORT_TYPE
Load_IR <= state.S_fet2.DB_MAX_OUTPUT_PORT_TYPE
Load_Add_R <= Select~8.DB_MAX_OUTPUT_PORT_TYPE
Load_Reg_Y <= Load_Reg_Y~0.DB_MAX_OUTPUT_PORT_TYPE
Load_Reg_Z <= Select~13.DB_MAX_OUTPUT_PORT_TYPE
Load_Carrier <= Load_Carrier~0.DB_MAX_OUTPUT_PORT_TYPE
write <= write~0.DB_MAX_OUTPUT_PORT_TYPE
instruction[0] => ~NO_FANOUT~
instruction[1] => ~NO_FANOUT~
instruction[2] => ~NO_FANOUT~
instruction[3] => ~NO_FANOUT~
instruction[4] => ~NO_FANOUT~
instruction[5] => ~NO_FANOUT~
instruction[6] => ~NO_FANOUT~
instruction[7] => ~NO_FANOUT~
instruction[8] => Decoder~1.IN1
instruction[9] => Decoder~1.IN0
instruction[10] => Decoder~0.IN1
instruction[11] => Decoder~0.IN0
instruction[12] => Decoder~2.IN3
instruction[13] => Decoder~2.IN2
instruction[14] => Decoder~2.IN1
instruction[15] => Decoder~2.IN0
zero => next_state.S_br1.IN3
zero => Sel_Bus_1.IN4
zero => Select~8.IN4
zero => next_state.S_fet1.IN3
Carrier_flag => Select~0.IN5
Carrier_flag => Select~2.IN5
Carrier_flag => Select~7.IN5
Carrier_flag => Select~1.IN2
clk => state~0.IN1
rst => state~1.IN1


|rsic|Memory_Unit:M2_SRAM
data_out[0] <= memory.DATAOUT
data_out[1] <= memory.DATAOUT1
data_out[2] <= memory.DATAOUT2
data_out[3] <= memory.DATAOUT3
data_out[4] <= memory.DATAOUT4
data_out[5] <= memory.DATAOUT5
data_out[6] <= memory.DATAOUT6
data_out[7] <= memory.DATAOUT7
data_out[8] <= memory.DATAOUT8
data_out[9] <= memory.DATAOUT9
data_out[10] <= memory.DATAOUT10
data_out[11] <= memory.DATAOUT11
data_out[12] <= memory.DATAOUT12
data_out[13] <= memory.DATAOUT13
data_out[14] <= memory.DATAOUT14
data_out[15] <= memory.DATAOUT15
data_in[0] => memory.DATAIN
data_in[1] => memory.DATAIN1
data_in[2] => memory.DATAIN2
data_in[3] => memory.DATAIN3
data_in[4] => memory.DATAIN4
data_in[5] => memory.DATAIN5
data_in[6] => memory.DATAIN6
data_in[7] => memory.DATAIN7
data_in[8] => memory.DATAIN8
data_in[9] => memory.DATAIN9
data_in[10] => memory.DATAIN10
data_in[11] => memory.DATAIN11
data_in[12] => memory.DATAIN12
data_in[13] => memory.DATAIN13
data_in[14] => memory.DATAIN14
data_in[15] => memory.DATAIN15
address[0] => memory.WADDR
address[0] => memory.RADDR
address[1] => memory.WADDR1
address[1] => memory.RADDR1
address[2] => memory.WADDR2
address[2] => memory.RADDR2
address[3] => memory.WADDR3
address[3] => memory.RADDR3
address[4] => memory.WADDR4
address[4] => memory.RADDR4
address[5] => memory.WADDR5
address[5] => memory.RADDR5
address[6] => memory.WADDR6
address[6] => memory.RADDR6
address[7] => memory.WADDR7
address[7] => memory.RADDR7
clk => memory.CLK0
write => memory.WE