rsic.hier_info

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_in[12] => data_out[12]~reg0.DATAIN
data_in[13] => data_out[13]~reg0.DATAIN
data_in[14] => data_out[14]~reg0.DATAIN
data_in[15] => data_out[15]~reg0.DATAIN
load => data_out[14]~reg0.ENA
load => data_out[13]~reg0.ENA
load => data_out[12]~reg0.ENA
load => data_out[11]~reg0.ENA
load => data_out[10]~reg0.ENA
load => data_out[9]~reg0.ENA
load => data_out[8]~reg0.ENA
load => data_out[7]~reg0.ENA
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[15]~reg0.ENA
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
rst => data_out[14]~reg0.ACLR
rst => data_out[13]~reg0.ACLR
rst => data_out[12]~reg0.ACLR
rst => data_out[11]~reg0.ACLR
rst => data_out[10]~reg0.ACLR
rst => data_out[9]~reg0.ACLR
rst => data_out[8]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|D_flop:Reg_Z
data_out <= data_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in => data_out~reg0.DATAIN
load => data_out~reg0.ENA
clk => data_out~reg0.CLK
rst => data_out~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|D_flop:Reg_C
data_out <= data_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in => data_out~reg0.DATAIN
load => data_out~reg0.ENA
clk => data_out~reg0.CLK
rst => data_out~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Address_Register:Add_R
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => ~NO_FANOUT~
data_in[9] => ~NO_FANOUT~
data_in[10] => ~NO_FANOUT~
data_in[11] => ~NO_FANOUT~
data_in[12] => ~NO_FANOUT~
data_in[13] => ~NO_FANOUT~
data_in[14] => ~NO_FANOUT~
data_in[15] => ~NO_FANOUT~
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[7]~reg0.ENA
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Instruction_Register:IR
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_in[12] => data_out[12]~reg0.DATAIN
data_in[13] => data_out[13]~reg0.DATAIN
data_in[14] => data_out[14]~reg0.DATAIN
data_in[15] => data_out[15]~reg0.DATAIN
load => data_out[14]~reg0.ENA
load => data_out[13]~reg0.ENA
load => data_out[12]~reg0.ENA
load => data_out[11]~reg0.ENA
load => data_out[10]~reg0.ENA
load => data_out[9]~reg0.ENA
load => data_out[8]~reg0.ENA
load => data_out[7]~reg0.ENA
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[15]~reg0.ENA
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
rst => data_out[14]~reg0.ACLR
rst => data_out[13]~reg0.ACLR
rst => data_out[12]~reg0.ACLR
rst => data_out[11]~reg0.ACLR
rst => data_out[10]~reg0.ACLR
rst => data_out[9]~reg0.ACLR
rst => data_out[8]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Program_Counter:PC
count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => count~31.DATAB
data_in[1] => count~30.DATAB
data_in[2] => count~29.DATAB
data_in[3] => count~28.DATAB
data_in[4] => count~27.DATAB
data_in[5] => count~26.DATAB
data_in[6] => count~25.DATAB
data_in[7] => count~24.DATAB
data_in[8] => ~NO_FANOUT~
data_in[9] => ~NO_FANOUT~
data_in[10] => ~NO_FANOUT~
data_in[11] => ~NO_FANOUT~
data_in[12] => ~NO_FANOUT~
data_in[13] => ~NO_FANOUT~
data_in[14] => ~NO_FANOUT~
data_in[15] => ~NO_FANOUT~
Load_PC => count~16.OUTPUTSELECT
Load_PC => count~17.OUTPUTSELECT
Load_PC => count~18.OUTPUTSELECT
Load_PC => count~19.OUTPUTSELECT
Load_PC => count~20.OUTPUTSELECT
Load_PC => count~21.OUTPUTSELECT
Load_PC => count~22.OUTPUTSELECT
Load_PC => count~23.OUTPUTSELECT
Load_PC => count~24.OUTPUTSELECT
Load_PC => count~25.OUTPUTSELECT
Load_PC => count~26.OUTPUTSELECT
Load_PC => count~27.OUTPUTSELECT
Load_PC => count~28.OUTPUTSELECT
Load_PC => count~29.OUTPUTSELECT
Load_PC => count~30.OUTPUTSELECT
Load_PC => count~31.OUTPUTSELECT
Inc_PC => count~0.OUTPUTSELECT
Inc_PC => count~1.OUTPUTSELECT
Inc_PC => count~2.OUTPUTSELECT
Inc_PC => count~3.OUTPUTSELECT
Inc_PC => count~4.OUTPUTSELECT
Inc_PC => count~5.OUTPUTSELECT
Inc_PC => count~6.OUTPUTSELECT
Inc_PC => count~7.OUTPUTSELECT
Inc_PC => count~8.OUTPUTSELECT
Inc_PC => count~9.OUTPUTSELECT
Inc_PC => count~10.OUTPUTSELECT
Inc_PC => count~11.OUTPUTSELECT
Inc_PC => count~12.OUTPUTSELECT
Inc_PC => count~13.OUTPUTSELECT
Inc_PC => count~14.OUTPUTSELECT
Inc_PC => count~15.OUTPUTSELECT
clk => count[14]~reg0.CLK
clk => count[13]~reg0.CLK
clk => count[12]~reg0.CLK
clk => count[11]~reg0.CLK
clk => count[10]~reg0.CLK
clk => count[9]~reg0.CLK
clk => count[8]~reg0.CLK
clk => count[7]~reg0.CLK
clk => count[6]~reg0.CLK
clk => count[5]~reg0.CLK
clk => count[4]~reg0.CLK
clk => count[3]~reg0.CLK
clk => count[2]~reg0.CLK
clk => count[1]~reg0.CLK
clk => count[0]~reg0.CLK
clk => count[15]~reg0.CLK
rst => count[14]~reg0.ACLR
rst => count[13]~reg0.ACLR
rst => count[12]~reg0.ACLR
rst => count[11]~reg0.ACLR
rst => count[10]~reg0.ACLR
rst => count[9]~reg0.ACLR
rst => count[8]~reg0.ACLR
rst => count[7]~reg0.ACLR
rst => count[6]~reg0.ACLR
rst => count[5]~reg0.ACLR
rst => count[4]~reg0.PRESET
rst => count[3]~reg0.ACLR
rst => count[2]~reg0.PRESET
rst => count[1]~reg0.ACLR
rst => count[0]~reg0.ACLR
rst => count[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Multiplexer_6ch:Mux_1
mux_out[0] <= mux_out~79.DB_MAX_OUTPUT_PORT_TYPE
mux_out[1] <= mux_out~78.DB_MAX_OUTPUT_PORT_TYPE
mux_out[2] <= mux_out~77.DB_MAX_OUTPUT_PORT_TYPE
mux_out[3] <= mux_out~76.DB_MAX_OUTPUT_PORT_TYPE
mux_out[4] <= mux_out~75.DB_MAX_OUTPUT_PORT_TYPE
mux_out[5] <= mux_out~74.DB_MAX_OUTPUT_PORT_TYPE
mux_out[6] <= mux_out~73.DB_MAX_OUTPUT_PORT_TYPE
mux_out[7] <= mux_out~72.DB_MAX_OUTPUT_PORT_TYPE
mux_out[8] <= mux_out~71.DB_MAX_OUTPUT_PORT_TYPE
mux_out[9] <= mux_out~70.DB_MAX_OUTPUT_PORT_TYPE
mux_out[10] <= mux_out~69.DB_MAX_OUTPUT_PORT_TYPE
mux_out[11] <= mux_out~68.DB_MAX_OUTPUT_PORT_TYPE
mux_out[12] <= mux_out~67.DB_MAX_OUTPUT_PORT_TYPE
mux_out[13] <= mux_out~66.DB_MAX_OUTPUT_PORT_TYPE
mux_out[14] <= mux_out~65.DB_MAX_OUTPUT_PORT_TYPE
mux_out[15] <= mux_out~64.DB_MAX_OUTPUT_PORT_TYPE
data_a[0] => mux_out~79.DATAB
data_a[1] => mux_out~78.DATAB
data_a[2] => mux_out~77.DATAB
data_a[3] => mux_out~76.DATAB
data_a[4] => mux_out~75.DATAB
data_a[5] => mux_out~74.DATAB
data_a[6] => mux_out~73.DATAB
data_a[7] => mux_out~72.DATAB
data_a[8] => mux_out~71.DATAB
data_a[9] => mux_out~70.DATAB
data_a[10] => mux_out~69.DATAB
data_a[11] => mux_out~68.DATAB
data_a[12] => mux_out~67.DATAB
data_a[13] => mux_out~66.DATAB
data_a[14] => mux_out~65.DATAB
data_a[15] => mux_out~64.DATAB
data_b[0] => mux_out~63.DATAB
data_b[1] => mux_out~62.DATAB
data_b[2] => mux_out~61.DATAB
data_b[3] => mux_out~60.DATAB
data_b[4] => mux_out~59.DATAB
data_b[5] => mux_out~58.DATAB
data_b[6] => mux_out~57.DATAB
data_b[7] => mux_out~56.DATAB
data_b[8] => mux_out~55.DATAB
data_b[9] => mux_out~54.DATAB
data_b[10] => mux_out~53.DATAB
data_b[11] => mux_out~52.DATAB
data_b[12] => mux_out~51.DATAB
data_b[13] => mux_out~50.DATAB
data_b[14] => mux_out~49.DATAB
data_b[15] => mux_out~48.DATAB
data_c[0] => mux_out~47.DATAB
data_c[1] => mux_out~46.DATAB
data_c[2] => mux_out~45.DATAB
data_c[3] => mux_out~44.DATAB
data_c[4] => mux_out~43.DATAB
data_c[5] => mux_out~42.DATAB
data_c[6] => mux_out~41.DATAB
data_c[7] => mux_out~40.DATAB
data_c[8] => mux_out~39.DATAB
data_c[9] => mux_out~38.DATAB
data_c[10] => mux_out~37.DATAB
data_c[11] => mux_out~36.DATAB
data_c[12] => mux_out~35.DATAB
data_c[13] => mux_out~34.DATAB
data_c[14] => mux_out~33.DATAB
data_c[15] => mux_out~32.DATAB
data_d[0] => mux_out~31.DATAB
data_d[1] => mux_out~30.DATAB
data_d[2] => mux_out~29.DATAB
data_d[3] => mux_out~28.DATAB
data_d[4] => mux_out~27.DATAB
data_d[5] => mux_out~26.DATAB
data_d[6] => mux_out~25.DATAB
data_d[7] => mux_out~24.DATAB
data_d[8] => mux_out~23.DATAB
data_d[9] => mux_out~22.DATAB
data_d[10] => mux_out~21.DATAB
data_d[11] => mux_out~20.DATAB
data_d[12] => mux_out~19.DATAB
data_d[13] => mux_out~18.DATAB
data_d[14] => mux_out~17.DATAB
data_d[15] => mux_out~16.DATAB
data_e[0] => mux_out~15.DATAB
data_e[1] => mux_out~14.DATAB
data_e[2] => mux_out~13.DATAB
data_e[3] => mux_out~12.DATAB
data_e[4] => mux_out~11.DATAB