rsic.hier_info

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

|rsic
clk => clk~0.IN3
rst => rst~0.IN2


|rsic|Processing_Unit:M0_Processor
instruction[0] <= instruction[0]~15.DB_MAX_OUTPUT_PORT_TYPE
instruction[1] <= instruction[1]~14.DB_MAX_OUTPUT_PORT_TYPE
instruction[2] <= instruction[2]~13.DB_MAX_OUTPUT_PORT_TYPE
instruction[3] <= instruction[3]~12.DB_MAX_OUTPUT_PORT_TYPE
instruction[4] <= instruction[4]~11.DB_MAX_OUTPUT_PORT_TYPE
instruction[5] <= instruction[5]~10.DB_MAX_OUTPUT_PORT_TYPE
instruction[6] <= instruction[6]~9.DB_MAX_OUTPUT_PORT_TYPE
instruction[7] <= instruction[7]~8.DB_MAX_OUTPUT_PORT_TYPE
instruction[8] <= instruction[8]~7.DB_MAX_OUTPUT_PORT_TYPE
instruction[9] <= instruction[9]~6.DB_MAX_OUTPUT_PORT_TYPE
instruction[10] <= instruction[10]~5.DB_MAX_OUTPUT_PORT_TYPE
instruction[11] <= instruction[11]~4.DB_MAX_OUTPUT_PORT_TYPE
instruction[12] <= instruction[12]~3.DB_MAX_OUTPUT_PORT_TYPE
instruction[13] <= instruction[13]~2.DB_MAX_OUTPUT_PORT_TYPE
instruction[14] <= instruction[14]~1.DB_MAX_OUTPUT_PORT_TYPE
instruction[15] <= instruction[15]~0.DB_MAX_OUTPUT_PORT_TYPE
Zflag <= D_flop:Reg_Z.port0
Carrier_flag <= D_flop:Reg_C.port0
address[0] <= Address_Register:Add_R.port0
address[1] <= Address_Register:Add_R.port0
address[2] <= Address_Register:Add_R.port0
address[3] <= Address_Register:Add_R.port0
address[4] <= Address_Register:Add_R.port0
address[5] <= Address_Register:Add_R.port0
address[6] <= Address_Register:Add_R.port0
address[7] <= Address_Register:Add_R.port0
Bus_1[0] <= Bus_1[0]~15.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[1] <= Bus_1[1]~14.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[2] <= Bus_1[2]~13.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[3] <= Bus_1[3]~12.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[4] <= Bus_1[4]~11.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[5] <= Bus_1[5]~10.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[6] <= Bus_1[6]~9.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[7] <= Bus_1[7]~8.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[8] <= Bus_1[8]~7.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[9] <= Bus_1[9]~6.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[10] <= Bus_1[10]~5.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[11] <= Bus_1[11]~4.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[12] <= Bus_1[12]~3.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[13] <= Bus_1[13]~2.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[14] <= Bus_1[14]~1.DB_MAX_OUTPUT_PORT_TYPE
Bus_1[15] <= Bus_1[15]~0.DB_MAX_OUTPUT_PORT_TYPE
mem_word[0] => mem_word[0]~15.IN1
mem_word[1] => mem_word[1]~14.IN1
mem_word[2] => mem_word[2]~13.IN1
mem_word[3] => mem_word[3]~12.IN1
mem_word[4] => mem_word[4]~11.IN1
mem_word[5] => mem_word[5]~10.IN1
mem_word[6] => mem_word[6]~9.IN1
mem_word[7] => mem_word[7]~8.IN1
mem_word[8] => mem_word[8]~7.IN1
mem_word[9] => mem_word[9]~6.IN1
mem_word[10] => mem_word[10]~5.IN1
mem_word[11] => mem_word[11]~4.IN1
mem_word[12] => mem_word[12]~3.IN1
mem_word[13] => mem_word[13]~2.IN1
mem_word[14] => mem_word[14]~1.IN1
mem_word[15] => mem_word[15]~0.IN1
Load_R0 => Load_R0~0.IN1
Load_R1 => Load_R1~0.IN1
Load_R2 => Load_R2~0.IN1
Load_R3 => Load_R3~0.IN1
Load_PC => Load_PC~0.IN1
Inc_PC => Inc_PC~0.IN1
Sel_Bus_1_Mux[0] => Sel_Bus_1_Mux[0]~2.IN1
Sel_Bus_1_Mux[1] => Sel_Bus_1_Mux[1]~1.IN1
Sel_Bus_1_Mux[2] => Sel_Bus_1_Mux[2]~0.IN1
Load_IR => Load_IR~0.IN1
Load_Add_R => Load_Add_R~0.IN1
Load_Reg_Y => Load_Reg_Y~0.IN1
Load_Reg_Z => Load_Reg_Z~0.IN1
Load_Carrier => Load_Carrier~0.IN1
Sel_Bus_2_Mux[0] => Sel_Bus_2_Mux[0]~1.IN1
Sel_Bus_2_Mux[1] => Sel_Bus_2_Mux[1]~0.IN1
clk => clk~0.IN10
rst => rst~0.IN10


|rsic|Processing_Unit:M0_Processor|Register_Unit:R0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_in[12] => data_out[12]~reg0.DATAIN
data_in[13] => data_out[13]~reg0.DATAIN
data_in[14] => data_out[14]~reg0.DATAIN
data_in[15] => data_out[15]~reg0.DATAIN
load => data_out[14]~reg0.ENA
load => data_out[13]~reg0.ENA
load => data_out[12]~reg0.ENA
load => data_out[11]~reg0.ENA
load => data_out[10]~reg0.ENA
load => data_out[9]~reg0.ENA
load => data_out[8]~reg0.ENA
load => data_out[7]~reg0.ENA
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[15]~reg0.ENA
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
rst => data_out[14]~reg0.ACLR
rst => data_out[13]~reg0.ACLR
rst => data_out[12]~reg0.ACLR
rst => data_out[11]~reg0.ACLR
rst => data_out[10]~reg0.ACLR
rst => data_out[9]~reg0.ACLR
rst => data_out[8]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Register_Unit:R1
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_in[12] => data_out[12]~reg0.DATAIN
data_in[13] => data_out[13]~reg0.DATAIN
data_in[14] => data_out[14]~reg0.DATAIN
data_in[15] => data_out[15]~reg0.DATAIN
load => data_out[14]~reg0.ENA
load => data_out[13]~reg0.ENA
load => data_out[12]~reg0.ENA
load => data_out[11]~reg0.ENA
load => data_out[10]~reg0.ENA
load => data_out[9]~reg0.ENA
load => data_out[8]~reg0.ENA
load => data_out[7]~reg0.ENA
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[15]~reg0.ENA
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
rst => data_out[14]~reg0.ACLR
rst => data_out[13]~reg0.ACLR
rst => data_out[12]~reg0.ACLR
rst => data_out[11]~reg0.ACLR
rst => data_out[10]~reg0.ACLR
rst => data_out[9]~reg0.ACLR
rst => data_out[8]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Register_Unit:R2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_in[12] => data_out[12]~reg0.DATAIN
data_in[13] => data_out[13]~reg0.DATAIN
data_in[14] => data_out[14]~reg0.DATAIN
data_in[15] => data_out[15]~reg0.DATAIN
load => data_out[14]~reg0.ENA
load => data_out[13]~reg0.ENA
load => data_out[12]~reg0.ENA
load => data_out[11]~reg0.ENA
load => data_out[10]~reg0.ENA
load => data_out[9]~reg0.ENA
load => data_out[8]~reg0.ENA
load => data_out[7]~reg0.ENA
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[15]~reg0.ENA
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
rst => data_out[14]~reg0.ACLR
rst => data_out[13]~reg0.ACLR
rst => data_out[12]~reg0.ACLR
rst => data_out[11]~reg0.ACLR
rst => data_out[10]~reg0.ACLR
rst => data_out[9]~reg0.ACLR
rst => data_out[8]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Register_Unit:R3
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_in[12] => data_out[12]~reg0.DATAIN
data_in[13] => data_out[13]~reg0.DATAIN
data_in[14] => data_out[14]~reg0.DATAIN
data_in[15] => data_out[15]~reg0.DATAIN
load => data_out[14]~reg0.ENA
load => data_out[13]~reg0.ENA
load => data_out[12]~reg0.ENA
load => data_out[11]~reg0.ENA
load => data_out[10]~reg0.ENA
load => data_out[9]~reg0.ENA
load => data_out[8]~reg0.ENA
load => data_out[7]~reg0.ENA
load => data_out[6]~reg0.ENA
load => data_out[5]~reg0.ENA
load => data_out[4]~reg0.ENA
load => data_out[3]~reg0.ENA
load => data_out[2]~reg0.ENA
load => data_out[1]~reg0.ENA
load => data_out[0]~reg0.ENA
load => data_out[15]~reg0.ENA
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
rst => data_out[14]~reg0.ACLR
rst => data_out[13]~reg0.ACLR
rst => data_out[12]~reg0.ACLR
rst => data_out[11]~reg0.ACLR
rst => data_out[10]~reg0.ACLR
rst => data_out[9]~reg0.ACLR
rst => data_out[8]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[15]~reg0.ACLR


|rsic|Processing_Unit:M0_Processor|Register_Unit:Reg_Y