rsic.map.rpt

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/rsic/rsic.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Jul 29 10:34:12 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rsic -c rsic
Warning: Can't analyze file -- file E:/rsic/rsic.v is missing
Info: Found 1 design units, including 1 entities, in source file RISC_SPM.v
    Info: Found entity 1: rsic
Warning (10273): Verilog HDL warning at Control_Unit.v(55): sign extended using "x" or "z"
Warning (10273): Verilog HDL warning at Control_Unit.v(59): sign extended using "x" or "z"
Info: Found 1 design units, including 1 entities, in source file Control_Unit.v
    Info: Found entity 1: Control_Unit
Info: Found 1 design units, including 1 entities, in source file Memory_Unit.v
    Info: Found entity 1: Memory_Unit
Warning (10273): Verilog HDL warning at Processing_Unit.v(134): sign extended using "x" or "z"
Warning (10273): Verilog HDL warning at Processing_Unit.v(145): sign extended using "x" or "z"
Info: Found 9 design units, including 9 entities, in source file Processing_Unit.v
    Info: Found entity 1: Processing_Unit
    Info: Found entity 2: Register_Unit
    Info: Found entity 3: D_flop
    Info: Found entity 4: Address_Register
    Info: Found entity 5: Instruction_Register
    Info: Found entity 6: Program_Counter
    Info: Found entity 7: Multiplexer_6ch
    Info: Found entity 8: Multiplexer_3ch
    Info: Found entity 9: Alu_RISC
Info: Elaborating entity "rsic" for the top level hierarchy
Info: Elaborating entity "Processing_Unit" for hierarchy "Processing_Unit:M0_Processor"
Info: Elaborating entity "Register_Unit" for hierarchy "Processing_Unit:M0_Processor|Register_Unit:R0"
Info: Elaborating entity "D_flop" for hierarchy "Processing_Unit:M0_Processor|D_flop:Reg_Z"
Info: Elaborating entity "Address_Register" for hierarchy "Processing_Unit:M0_Processor|Address_Register:Add_R"
Info: Elaborating entity "Instruction_Register" for hierarchy "Processing_Unit:M0_Processor|Instruction_Register:IR"
Info: Elaborating entity "Program_Counter" for hierarchy "Processing_Unit:M0_Processor|Program_Counter:PC"
Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(118): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "Multiplexer_6ch" for hierarchy "Processing_Unit:M0_Processor|Multiplexer_6ch:Mux_1"
Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(129): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "Multiplexer_3ch" for hierarchy "Processing_Unit:M0_Processor|Multiplexer_3ch:Mux_2"
Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(143): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "Alu_RISC" for hierarchy "Processing_Unit:M0_Processor|Alu_RISC:ALU"
Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(167): object "RD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(168): object "WR" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(169): object "ID_WR" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(170): object "BR" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(174): object "ID_RD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(177): object "BRC" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(198): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(199): truncated value with size 32 to match size of target (16)
Warning (10240): Verilog HDL Always Construct warning at Processing_Unit.v(190): variable "alu_out" may not be assigned a new value in every possible path through the Always Construct.  Variable "alu_out" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at Processing_Unit.v(190): variable "carrier" may not be assigned a new value in every possible path through the Always Construct.  Variable "carrier" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "Control_Unit" for hierarchy "Control_Unit:M1_Controller"
Warning (10036): Verilog HDL or VHDL warning at Control_Unit.v(11): object "address_size" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Control_Unit.v(42): object "err_flag" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Control_Unit.v(47): object "address" assigned a value but never read
Warning (10273): Verilog HDL warning at Control_Unit.v(54): sign extended using "x" or "z"
Warning (10230): Verilog HDL assignment warning at Control_Unit.v(50): truncated value with size 32 to match size of target (3)
Warning (10273): Verilog HDL warning at Control_Unit.v(58): sign extended using "x" or "z"
Warning (10230): Verilog HDL assignment warning at Control_Unit.v(57): truncated value with size 32 to match size of target (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(99): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(100): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(105): variable "src" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(106): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(107): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(108): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(109): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(114): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(119): variable "src" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(120): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(121): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(122): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(123): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(129): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(132): variable "dest" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(133): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(134): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(135): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(136): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(163): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(168): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(173): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(176): variable "src" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(177): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(178): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(179): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(180): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(186): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(189): variable "dest" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(190): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(191): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(192): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(193): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(201): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(206): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(208): variable "dest" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(209): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(210): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(211): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(212): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(217): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(219): variable "Carrier_flag" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(240): variable "dest" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(241): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(242): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(243): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(244): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(252): variable "dest" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(253): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(254): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(255): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(256): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(264): variable "src" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(265): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(266): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(267): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(268): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(295): variable "dest" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(296): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(297): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(298): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(299): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at Control_Unit.v(306): variable "src" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(307): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Case Statement warning at Control_Unit.v(308): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10271): Verilog HDL Cas