myclk.tan.qmsg

两位独立数码管100进制计数器

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "y\[0\]\$latch " "Warning: Node \"y\[0\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "y\[1\]\$latch " "Warning: Node \"y\[1\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "y\[2\]\$latch " "Warning: Node \"y\[2\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "y\[3\]\$latch " "Warning: Node \"y\[3\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "y\[4\]\$latch " "Warning: Node \"y\[4\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "y\[5\]\$latch " "Warning: Node \"y\[5\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "y\[6\]\$latch " "Warning: Node \"y\[6\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[0\]\$latch " "Warning: Node \"yy\[0\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[1\]\$latch " "Warning: Node \"yy\[1\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[2\]\$latch " "Warning: Node \"yy\[2\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[3\]\$latch " "Warning: Node \"yy\[3\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[4\]\$latch " "Warning: Node \"yy\[4\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[5\]\$latch " "Warning: Node \"yy\[5\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "yy\[6\]\$latch " "Warning: Node \"yy\[6\]\$latch\" is a latch" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 4 -1 0 } } { "f:/quartus/win/Assignment Editor.qase" "" { Assignment "f:/quartus/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\] register c\[2\] 89.29 MHz 11.2 ns Internal " "Info: Clock \"clk\" has Internal fmax of 89.29 MHz between source register \"lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\]\" and destination register \"c\[2\]\" (period= 11.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.800 ns + Longest register register " "Info: + Longest register to register delay is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_G21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_G21; Fanout = 3; REG Node = 'lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.500 ns) 2.800 ns lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~47 2 COMB LC3_G19 1 " "Info: 2: + IC(1.300 ns) + CELL(1.500 ns) = 2.800 ns; Loc. = LC3_G19; Fanout = 1; COMB Node = 'lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~47'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "2.800 ns" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 4.400 ns LessThan0~55 3 COMB LC2_G19 12 " "Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC2_G19; Fanout = 12; COMB Node = 'LessThan0~55'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.600 ns" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47 LessThan0~55 } "NODE_NAME" } } { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 6.000 ns lpm_counter:b_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~1 4 COMB LC1_G19 6 " "Info: 4: + IC(0.200 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC1_G19; Fanout = 6; COMB Node = 'lpm_counter:b_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~1'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.600 ns" { LessThan0~55 lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.400 ns) 8.700 ns c\[2\]~173 5 COMB LC8_G20 4 " "Info: 5: + IC(1.300 ns) + CELL(1.400 ns) = 8.700 ns; Loc. = LC8_G20; Fanout = 4; COMB Node = 'c\[2\]~173'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "2.700 ns" { lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 c[2]~173 } "NODE_NAME" } } { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 9.800 ns c\[2\] 6 REG LC5_G20 19 " "Info: 6: + IC(0.200 ns) + CELL(0.900 ns) = 9.800 ns; Loc. = LC5_G20; Fanout = 19; REG Node = 'c\[2\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.100 ns" { c[2]~173 c[2] } "NODE_NAME" } } { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns ( 67.35 % ) " "Info: Total cell delay = 6.600 ns ( 67.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 32.65 % ) " "Info: Total interconnect delay = 3.200 ns ( 32.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "9.800 ns" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47 LessThan0~55 lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 c[2]~173 c[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "9.800 ns" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47 LessThan0~55 lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 c[2]~173 c[2] } { 0.000ns 1.300ns 0.200ns 0.200ns 1.300ns 0.200ns } { 0.000ns 1.500ns 1.400ns 1.400ns 1.400ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 19 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns c\[2\] 2 REG LC5_G20 19 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_G20; Fanout = 19; REG Node = 'c\[2\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk c[2] } "NODE_NAME" } } { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk c[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out c[2] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 19 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_G21 3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_G21; Fanout = 3; REG Node = 'lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk c[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out c[2] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "9.800 ns" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47 LessThan0~55 lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 c[2]~173 c[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "9.800 ns" { lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47 LessThan0~55 lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 c[2]~173 c[2] } { 0.000ns 1.300ns 0.200ns 0.200ns 1.300ns 0.200ns } { 0.000ns 1.500ns 1.400ns 1.400ns 1.400ns 0.900ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk c[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out c[2] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 16 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 17:42:51 2009 " "Info: Processing ended: Mon Mar 30 17:42:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}