myclk.map.qmsg

两位独立数码管100进制计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 17:42:15 2009 " "Info: Processing started: Mon Mar 30 17:42:15 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myclk -c myclk " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myclk -c myclk" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myclk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file myclk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 myclk-bhv " "Info: Found design unit 1: myclk-bhv" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 myclk " "Info: Found entity 1: myclk" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "myclk " "Info: Elaborating entity \"myclk\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y myclk.vhd(34) " "Warning (10631): VHDL Process Statement warning at myclk.vhd(34): inferring latch(es) for signal or variable \"y\", which holds its previous value in one or more paths through the process" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "yy myclk.vhd(58) " "Warning (10631): VHDL Process Statement warning at myclk.vhd(58): inferring latch(es) for signal or variable \"yy\", which holds its previous value in one or more paths through the process" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[0\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[0\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[1\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[1\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[2\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[2\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[3\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[3\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[4\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[4\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[5\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[5\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "yy\[6\] myclk.vhd(58) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for \"yy\[6\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 58 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[0\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[0\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[1\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[1\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[2\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[2\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[3\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[3\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[4\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[4\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[5\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[5\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y\[6\] myclk.vhd(34) " "Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for \"y\[6\]\"" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 34 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "b\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"b\[0\]~4\"" {  } { { "myclk.vhd" "b\[0\]~4" { Text "H:/VHDL/myclk/myclk.vhd" 18 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "\\t1:a\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"\\t1:a\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/quartus/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:b_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:b_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_counter:b_rtl_0\|alt_counter_f10ke:wysi_counter lpm_counter:b_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:b_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"lpm_counter:b_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "f:/quartus/libraries/megafunctions/lpm_counter.tdf" 417 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:b_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:b_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:\\t1:a\[0\]_rtl_1 " "Info: Elaborated megafunction instantiation \"lpm_counter:\\t1:a\[0\]_rtl_1\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter lpm_counter:\\t1:a\[0\]_rtl_1 " "Info: Elaborated megafunction instantiation \"lpm_counter:\\t1:a\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"lpm_counter:\\t1:a\[0\]_rtl_1\"" {  } { { "lpm_counter.tdf" "" { Text "f:/quartus/libraries/megafunctions/lpm_counter.tdf" 417 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:\\t1:a\[0\]_rtl_1 " "Info: Instantiated megafunction \"lpm_counter:\\t1:a\[0\]_rtl_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ds4 GND " "Warning: Pin \"ds4\" stuck at GND" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 5 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ds5 GND " "Warning: Pin \"ds5\" stuck at GND" {  } { { "myclk.vhd" "" { Text "H:/VHDL/myclk/myclk.vhd" 5 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "88 " "Info: Implemented 88 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "71 " "Info: Implemented 71 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 17:42:22 2009 " "Info: Processing ended: Mon Mar 30 17:42:22 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}