📄 myclk.map.rpt
字号:
; y[1]$latch ; GND ; yes ;
; y[2]$latch ; GND ; yes ;
; y[3]$latch ; GND ; yes ;
; y[4]$latch ; GND ; yes ;
; y[5]$latch ; GND ; yes ;
; y[6]$latch ; GND ; yes ;
; yy[0]$latch ; GND ; yes ;
; yy[1]$latch ; GND ; yes ;
; yy[2]$latch ; GND ; yes ;
; yy[3]$latch ; GND ; yes ;
; yy[4]$latch ; GND ; yes ;
; yy[5]$latch ; GND ; yes ;
; yy[6]$latch ; GND ; yes ;
; Number of user-specified and inferred latches = 14 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 16 ;
; Number of registers using Synchronous Clear ; 12 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------+
; Source assignments for Top-level Entity: |myclk ;
+----------------+-------+------+-----------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+-----------------+
; POWER_UP_LEVEL ; Low ; - ; c[0] ;
; POWER_UP_LEVEL ; Low ; - ; c[1] ;
; POWER_UP_LEVEL ; Low ; - ; c[2] ;
; POWER_UP_LEVEL ; Low ; - ; c[3] ;
; POWER_UP_LEVEL ; Low ; - ; b[0] ;
; POWER_UP_LEVEL ; Low ; - ; b[1] ;
; POWER_UP_LEVEL ; Low ; - ; b[2] ;
; POWER_UP_LEVEL ; Low ; - ; b[3] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[0] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[1] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[2] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[3] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[4] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[5] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[6] ;
; POWER_UP_LEVEL ; Low ; - ; t1:a[7] ;
+----------------+-------+------+-----------------+
+----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:b_rtl_0 ;
+------------------------+-------------------+-------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:\t1:a[0]_rtl_1 ;
+------------------------+-------------------+--------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+--------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 8 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Mar 30 17:42:15 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myclk -c myclk
Info: Found 2 design units, including 1 entities, in source file myclk.vhd
Info: Found design unit 1: myclk-bhv
Info: Found entity 1: myclk
Info: Elaborating entity "myclk" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at myclk.vhd(34): inferring latch(es) for signal or variable "y", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at myclk.vhd(58): inferring latch(es) for signal or variable "yy", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[0]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[1]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[2]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[3]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[4]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[5]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(58): inferred latch for "yy[6]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[0]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[1]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[2]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[3]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[4]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[5]"
Info (10041): Verilog HDL or VHDL info at myclk.vhd(34): inferred latch for "y[6]"
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "b[0]~4"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "\t1:a[0]~0"
Info: Found 1 design units, including 1 entities, in source file f:/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:b_rtl_0"
Info: Found 1 design units, including 1 entities, in source file f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:b_rtl_0"
Info: Instantiated megafunction "lpm_counter:b_rtl_0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "4"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "lpm_counter:\t1:a[0]_rtl_1"
Info: Elaborated megafunction instantiation "lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:\t1:a[0]_rtl_1"
Info: Instantiated megafunction "lpm_counter:\t1:a[0]_rtl_1" with the following parameter:
Info: Parameter "LPM_WIDTH" = "8"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "ds4" stuck at GND
Warning: Pin "ds5" stuck at GND
Info: Implemented 88 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 16 output pins
Info: Implemented 71 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Mon Mar 30 17:42:22 2009
Info: Elapsed time: 00:00:07
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -