myclk.tan.rpt

两位独立数码管100进制计数器

; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4] ; clk        ; clk      ; None                        ; None                      ; 1.000 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; clk        ; clk      ; None                        ; None                      ; 1.000 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; clk        ; clk      ; None                        ; None                      ; 1.000 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0]        ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[1]        ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0]        ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0]        ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
+-------+------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Mar 30 17:42:48 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myclk -c myclk
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "y[0]$latch" is a latch
    Warning: Node "y[1]$latch" is a latch
    Warning: Node "y[2]$latch" is a latch
    Warning: Node "y[3]$latch" is a latch
    Warning: Node "y[4]$latch" is a latch
    Warning: Node "y[5]$latch" is a latch
    Warning: Node "y[6]$latch" is a latch
    Warning: Node "yy[0]$latch" is a latch
    Warning: Node "yy[1]$latch" is a latch
    Warning: Node "yy[2]$latch" is a latch
    Warning: Node "yy[3]$latch" is a latch
    Warning: Node "yy[4]$latch" is a latch
    Warning: Node "yy[5]$latch" is a latch
    Warning: Node "yy[6]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 89.29 MHz between source register "lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4]" and destination register "c[2]" (period= 11.2 ns)
    Info: + Longest register to register delay is 9.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_G21; Fanout = 3; REG Node = 'lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4]'
        Info: 2: + IC(1.300 ns) + CELL(1.500 ns) = 2.800 ns; Loc. = LC3_G19; Fanout = 1; COMB Node = 'lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~47'
        Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC2_G19; Fanout = 12; COMB Node = 'LessThan0~55'
        Info: 4: + IC(0.200 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC1_G19; Fanout = 6; COMB Node = 'lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1'
        Info: 5: + IC(1.300 ns) + CELL(1.400 ns) = 8.700 ns; Loc. = LC8_G20; Fanout = 4; COMB Node = 'c[2]~173'
        Info: 6: + IC(0.200 ns) + CELL(0.900 ns) = 9.800 ns; Loc. = LC5_G20; Fanout = 19; REG Node = 'c[2]'
        Info: Total cell delay = 6.600 ns ( 67.35 % )
        Info: Total interconnect delay = 3.200 ns ( 32.65 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_G20; Fanout = 19; REG Node = 'c[2]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
        Info: - Longest clock path from clock "clk" to source register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_G21; Fanout = 3; REG Node = 'lpm_counter:\t1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[4]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: Quartus II Timing Analyzer was successful. 0 errors, 16 warnings
    Info: Processing ended: Mon Mar 30 17:42:51 2009
    Info: Elapsed time: 00:00:03