myled4.tan.qmsg

四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL

{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[0\] y\[0\]~reg0 11.000 ns register " "Info: tco from clock \"clk\" to destination pin \"y\[0\]\" through register \"y\[0\]~reg0\" is 11.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 62 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 62; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns y\[0\]~reg0 2 REG LC1_F15 4 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_F15; Fanout = 4; REG Node = 'y\[0\]~reg0'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk y[0]~reg0 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[0]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out y[0]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register pin " "Info: + Longest register to pin delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[0\]~reg0 1 REG LC1_F15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F15; Fanout = 4; REG Node = 'y\[0\]~reg0'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { y[0]~reg0 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(4.600 ns) 6.800 ns y\[0\] 2 PIN PIN_150 0 " "Info: 2: + IC(2.200 ns) + CELL(4.600 ns) = 6.800 ns; Loc. = PIN_150; Fanout = 0; PIN Node = 'y\[0\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "6.800 ns" { y[0]~reg0 y[0] } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 67.65 % ) " "Info: Total cell delay = 4.600 ns ( 67.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 32.35 % ) " "Info: Total interconnect delay = 2.200 ns ( 32.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "6.800 ns" { y[0]~reg0 y[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "6.800 ns" { y[0]~reg0 y[0] } { 0.000ns 2.200ns } { 0.000ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[0]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out y[0]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "6.800 ns" { y[0]~reg0 y[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "6.800 ns" { y[0]~reg0 y[0] } { 0.000ns 2.200ns } { 0.000ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "clear_en key\[1\] clk -6.100 ns register " "Info: th for register \"clear_en\" (data pin = \"key\[1\]\", clock pin = \"clk\") is -6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 62 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 62; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns clear_en 2 REG LC7_F23 6 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_F23; Fanout = 6; REG Node = 'clear_en'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk clear_en } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out clear_en } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns key\[1\] 1 PIN PIN_40 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_40; Fanout = 3; PIN Node = 'key\[1\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { key[1] } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(1.500 ns) 9.300 ns clear_en~60 2 COMB LC3_F23 1 " "Info: 2: + IC(4.800 ns) + CELL(1.500 ns) = 9.300 ns; Loc. = LC3_F23; Fanout = 1; COMB Node = 'clear_en~60'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "6.300 ns" { key[1] clear_en~60 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 10.400 ns clear_en 3 REG LC7_F23 6 " "Info: 3: + IC(0.200 ns) + CELL(0.900 ns) = 10.400 ns; Loc. = LC7_F23; Fanout = 6; REG Node = 'clear_en'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.100 ns" { clear_en~60 clear_en } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns ( 51.92 % ) " "Info: Total cell delay = 5.400 ns ( 51.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns ( 48.08 % ) " "Info: Total interconnect delay = 5.000 ns ( 48.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "10.400 ns" { key[1] clear_en~60 clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "10.400 ns" { key[1] key[1]~out clear_en~60 clear_en } { 0.000ns 0.000ns 4.800ns 0.200ns } { 0.000ns 3.000ns 1.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out clear_en } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "10.400 ns" { key[1] clear_en~60 clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "10.400 ns" { key[1] key[1]~out clear_en~60 clear_en } { 0.000ns 0.000ns 4.800ns 0.200ns } { 0.000ns 3.000ns 1.500ns 0.900ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 10 09:41:02 2009 " "Info: Processing ended: Fri Apr 10 09:41:02 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}