myled4.tan.qmsg

四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 6 -1 0 } } { "f:/quartus/win/Assignment Editor.qase" "" { Assignment "f:/quartus/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register \\a2:n\[0\] register y\[6\]~reg0 55.87 MHz 17.9 ns Internal " "Info: Clock \"clk\" has Internal fmax of 55.87 MHz between source register \"\\a2:n\[0\]\" and destination register \"y\[6\]~reg0\" (period= 17.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.500 ns + Longest register register " "Info: + Longest register to register delay is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\a2:n\[0\] 1 REG LC6_F5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_F5; Fanout = 8; REG Node = '\\a2:n\[0\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { \a2:n[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.600 ns) 1.800 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC2_F7 2 " "Info: 2: + IC(1.200 ns) + CELL(0.600 ns) = 1.800 ns; Loc. = LC2_F7; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.800 ns" { \a2:n[0] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.900 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC3_F7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 1.900 ns; Loc. = LC3_F7; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.000 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC4_F7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC4_F7; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.100 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC5_F7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 2.100 ns; Loc. = LC5_F7; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.200 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC6_F7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 2.200 ns; Loc. = LC6_F7; Fanout = 1; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.500 ns lpm_add_sub:Add5\|addcore:adder\|unreg_res_node\[6\] 7 COMB LC7_F7 2 " "Info: 7: + IC(0.000 ns) + CELL(1.300 ns) = 3.500 ns; Loc. = LC7_F7; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|unreg_res_node\[6\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] } "NODE_NAME" } } { "addcore.tdf" "" { Text "f:/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 6.100 ns Equal11~50 8 COMB LC4_F6 5 " "Info: 8: + IC(1.200 ns) + CELL(1.400 ns) = 6.100 ns; Loc. = LC4_F6; Fanout = 5; COMB Node = 'Equal11~50'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "2.600 ns" { lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal11~50 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 7.900 ns Equal0~34 9 COMB LC2_F6 16 " "Info: 9: + IC(0.200 ns) + CELL(1.600 ns) = 7.900 ns; Loc. = LC2_F6; Fanout = 16; COMB Node = 'Equal0~34'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.800 ns" { Equal11~50 Equal0~34 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.500 ns) 10.500 ns y\[0\]~8525 10 COMB LC8_F5 7 " "Info: 10: + IC(1.100 ns) + CELL(1.500 ns) = 10.500 ns; Loc. = LC8_F5; Fanout = 7; COMB Node = 'y\[0\]~8525'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "2.600 ns" { Equal0~34 y[0]~8525 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 12.100 ns y\[0\]~8582 11 COMB LC1_F5 1 " "Info: 11: + IC(0.200 ns) + CELL(1.400 ns) = 12.100 ns; Loc. = LC1_F5; Fanout = 1; COMB Node = 'y\[0\]~8582'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.600 ns" { y[0]~8525 y[0]~8582 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 13.700 ns y\[0\]~8585 12 COMB LC3_F5 1 " "Info: 12: + IC(0.200 ns) + CELL(1.400 ns) = 13.700 ns; Loc. = LC3_F5; Fanout = 1; COMB Node = 'y\[0\]~8585'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.600 ns" { y[0]~8582 y[0]~8585 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 15.300 ns y\[0\]~8588 13 COMB LC7_F5 1 " "Info: 13: + IC(0.200 ns) + CELL(1.400 ns) = 15.300 ns; Loc. = LC7_F5; Fanout = 1; COMB Node = 'y\[0\]~8588'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.600 ns" { y[0]~8585 y[0]~8588 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 16.500 ns y\[6\]~reg0 14 REG LC5_F5 4 " "Info: 14: + IC(0.200 ns) + CELL(1.000 ns) = 16.500 ns; Loc. = LC5_F5; Fanout = 4; REG Node = 'y\[6\]~reg0'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.200 ns" { y[0]~8588 y[6]~reg0 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns ( 72.73 % ) " "Info: Total cell delay = 12.000 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 27.27 % ) " "Info: Total interconnect delay = 4.500 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "16.500 ns" { \a2:n[0] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal11~50 Equal0~34 y[0]~8525 y[0]~8582 y[0]~8585 y[0]~8588 y[6]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "16.500 ns" { \a2:n[0] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal11~50 Equal0~34 y[0]~8525 y[0]~8582 y[0]~8585 y[0]~8588 y[6]~reg0 } { 0.000ns 1.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.200ns 0.200ns 1.100ns 0.200ns 0.200ns 0.200ns 0.200ns } { 0.000ns 0.600ns 0.100ns 0.100ns 0.100ns 0.100ns 1.300ns 1.400ns 1.600ns 1.500ns 1.400ns 1.400ns 1.400ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 62 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 62; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns y\[6\]~reg0 2 REG LC5_F5 4 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_F5; Fanout = 4; REG Node = 'y\[6\]~reg0'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk y[6]~reg0 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[6]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out y[6]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 62 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 62; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns \\a2:n\[0\] 2 REG LC6_F5 8 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC6_F5; Fanout = 8; REG Node = '\\a2:n\[0\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk \a2:n[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \a2:n[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out \a2:n[0] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[6]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out y[6]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \a2:n[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out \a2:n[0] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "16.500 ns" { \a2:n[0] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal11~50 Equal0~34 y[0]~8525 y[0]~8582 y[0]~8585 y[0]~8588 y[6]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "16.500 ns" { \a2:n[0] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal11~50 Equal0~34 y[0]~8525 y[0]~8582 y[0]~8585 y[0]~8588 y[6]~reg0 } { 0.000ns 1.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.200ns 0.200ns 1.100ns 0.200ns 0.200ns 0.200ns 0.200ns } { 0.000ns 0.600ns 0.100ns 0.100ns 0.100ns 0.100ns 1.300ns 1.400ns 1.600ns 1.500ns 1.400ns 1.400ns 1.400ns 1.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[6]~reg0 } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out y[6]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \a2:n[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out \a2:n[0] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "clear_en key\[3\] clk 7.800 ns register " "Info: tsu for register \"clear_en\" (data pin = \"key\[3\]\", clock pin = \"clk\") is 7.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.600 ns + Longest pin register " "Info: + Longest pin to register delay is 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns key\[3\] 1 PIN PIN_44 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_44; Fanout = 3; PIN Node = 'key\[3\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { key[3] } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(1.600 ns) 9.500 ns clear_en~60 2 COMB LC3_F23 1 " "Info: 2: + IC(4.900 ns) + CELL(1.600 ns) = 9.500 ns; Loc. = LC3_F23; Fanout = 1; COMB Node = 'clear_en~60'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "6.500 ns" { key[3] clear_en~60 } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 10.600 ns clear_en 3 REG LC7_F23 6 " "Info: 3: + IC(0.200 ns) + CELL(0.900 ns) = 10.600 ns; Loc. = LC7_F23; Fanout = 6; REG Node = 'clear_en'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.100 ns" { clear_en~60 clear_en } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 51.89 % ) " "Info: Total cell delay = 5.500 ns ( 51.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 48.11 % ) " "Info: Total interconnect delay = 5.100 ns ( 48.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "10.600 ns" { key[3] clear_en~60 clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "10.600 ns" { key[3] key[3]~out clear_en~60 clear_en } { 0.000ns 0.000ns 4.900ns 0.200ns } { 0.000ns 3.000ns 1.600ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 62 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 62; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns clear_en 2 REG LC7_F23 6 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_F23; Fanout = 6; REG Node = 'clear_en'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk clear_en } "NODE_NAME" } } { "myled4.vhd" "" { Text "H:/VHDL/myled4/myled4.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out clear_en } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "10.600 ns" { key[3] clear_en~60 clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "10.600 ns" { key[3] key[3]~out clear_en~60 clear_en } { 0.000ns 0.000ns 4.900ns 0.200ns } { 0.000ns 3.000ns 1.600ns 0.900ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk clear_en } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out clear_en } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}