adcint.vhd

用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL

library ieee;
use ieee.std_logic_1164.all;
entity adcint is
   port(  d:in std_logic_vector(7 downto 0); --来自0809转换好的8位数据
        clk:in std_logic;                    --状态机工作时钟
        eoc:in std_logic;                    --转换状态指示，低电平表示正在转换
        ale:out std_logic;                   --8位模拟信号通道地址锁存信号
      start:out std_logic;                   --转换开始信号
         oe:out std_logic;                   --数据输出三太控制信号
       adda:out std_logic;                   --信号通道最低位控制信号
      lock0:out std_logic;                   --观察数据锁存时钟
          q:out std_logic_vector(7 downto 0));--8位数据输出
end adcint;
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architecture bhv of adcint is
type states is (st0,st1,st2,st3,st4);      --定义各状态子类型
  signal current_state,next_state:states :=st0;
  signal regl:std_logic_vector(7 downto 0);
  signal lock:std_logic;                  --转换后数据输出锁存时钟信号
 begin
  adda<='1';   --当adda<='0',模拟信号通道in0;当adda<='1',则进入通道in1
   q<=regl;lock0<=lock;
com:process(current_state,eoc) --规定各状态转换方式
     begin
      case current_state is
        when st0 => ale<='0';start<='0';lock<='0';oe<='0';
                  next_state<=st1;
        when st1 => ale<='1';start<='1';lock<='0';oe<='0';
                   next_state<=st2;
        when st2 => ale<='0';start<='0';lock<='0';oe<='0';
              if (eoc<='1') then next_state<=st3; --eoc=1表明转换结束
               else next_state<=st2;              --转换未结束，继续等待
              end if;
        when st3 => ale<='0';start<='0';lock<='0';oe<='1';
                 next_state <=st4;             --开启oe，输出转换好的数据
        when st4 => ale<='0';start<='0';lock<='1';oe<='1';
                next_state<=st0;
        when others =>next_state<=st0;
       end case;
 end process com;
reg:process(clk)
    begin
       if (clk'event and clk='1') then 
          current_state<=next_state;
       end if;
end process reg;  --由信号current_state将当前状态值带出reg进程
latch1:process(lock) --此进程中，在lock的上升沿，将转换好的数据锁入
       begin
         if lock='1' and lock'event then 
               regl<=d;
         end if;
end process latch1;
end bhv;