immap_qe.h

u-boot1.3德国DENX小组开发的用于多种嵌入式CPU的bootloader

	u32 miimstat;		/* MII management status reg           */
	u32 miimind;		/* MII management indication reg       */
	u32 ifctl;		/* interface control reg               */
	u32 ifstat;		/* interface statux reg                */
} __attribute__ ((packed))uec_mii_t;

typedef struct ucc_ethernet {
	u32 maccfg1;		/* mac configuration reg. 1            */
	u32 maccfg2;		/* mac configuration reg. 2            */
	u32 ipgifg;		/* interframe gap reg.                 */
	u32 hafdup;		/* half-duplex reg.                    */
	u8 res1[0x10];
	u32 miimcfg;		/* MII management configuration reg    */
	u32 miimcom;		/* MII management command reg          */
	u32 miimadd;		/* MII management address reg          */
	u32 miimcon;		/* MII management control reg          */
	u32 miimstat;		/* MII management status reg           */
	u32 miimind;		/* MII management indication reg       */
	u32 ifctl;		/* interface control reg               */
	u32 ifstat;		/* interface statux reg                */
	u32 macstnaddr1;	/* mac station address part 1 reg      */
	u32 macstnaddr2;	/* mac station address part 2 reg      */
	u8 res2[0x8];
	u32 uempr;		/* UCC Ethernet Mac parameter reg      */
	u32 utbipar;		/* UCC tbi address reg                 */
	u16 uescr;		/* UCC Ethernet statistics control reg */
	u8 res3[0x180 - 0x15A];
	u32 tx64;		/* Total number of frames (including bad
				 * frames) transmitted that were exactly
				 * of the minimal length (64 for un tagged,
				 * 68 for tagged, or with length exactly
				 * equal to the parameter MINLength */
	u32 tx127;		/* Total number of frames (including bad
				 * frames) transmitted that were between
				 * MINLength (Including FCS length==4)
				 * and 127 octets */
	u32 tx255;		/* Total number of frames (including bad
				 * frames) transmitted that were between
				 * 128 (Including FCS length==4) and 255
				 * octets */
	u32 rx64;		/* Total number of frames received including
				 * bad frames that were exactly of the
				 * mninimal length (64 bytes) */
	u32 rx127;		/* Total number of frames (including bad
				 * frames) received that were between
				 * MINLength (Including FCS length==4)
				 * and 127 octets */
	u32 rx255;		/* Total number of frames (including
				 * bad frames) received that were between
				 * 128 (Including FCS length==4) and 255
				 * octets */
	u32 txok;		/* Total number of octets residing in frames
				 * that where involved in succesfull
				 * transmission */
	u16 txcf;		/* Total number of PAUSE control frames
				 *  transmitted by this MAC */
	u8 res4[0x2];
	u32 tmca;		/* Total number of frames that were transmitted
				 * succesfully with the group address bit set
				 * that are not broadcast frames */
	u32 tbca;		/* Total number of frames transmitted
				 * succesfully that had destination address
				 * field equal to the broadcast address */
	u32 rxfok;		/* Total number of frames received OK */
	u32 rxbok;		/* Total number of octets received OK */
	u32 rbyt;		/* Total number of octets received including
				 * octets in bad frames. Must be implemented
				 * in HW because it includes octets in frames
				 * that never even reach the UCC */
	u32 rmca;		/* Total number of frames that were received
				 * succesfully with the group address bit set
				 * that are not broadcast frames */
	u32 rbca;		/* Total number of frames received succesfully
				 * that had destination address equal to the
				 * broadcast address */
	u32 scar;		/* Statistics carry register */
	u32 scam;		/* Statistics caryy mask register */
	u8 res5[0x200 - 0x1c4];
} __attribute__ ((packed)) uec_t;

/* QE UCC Fast
*/
typedef struct ucc_fast {
	u32 gumr;		/* UCCx general mode register */
	u32 upsmr;		/* UCCx protocol-specific mode register  */
	u16 utodr;		/* UCCx transmit on demand register  */
	u8 res0[0x2];
	u16 udsr;		/* UCCx data synchronization register  */
	u8 res1[0x2];
	u32 ucce;		/* UCCx event register */
	u32 uccm;		/* UCCx mask register.  */
	u8 uccs;		/* UCCx status register */
	u8 res2[0x7];
	u32 urfb;		/* UCC receive FIFO base */
	u16 urfs;		/* UCC receive FIFO size */
	u8 res3[0x2];
	u16 urfet;		/* UCC receive FIFO emergency threshold */
	u16 urfset;		/* UCC receive FIFO special emergency
				 * threshold */
	u32 utfb;		/* UCC transmit FIFO base */
	u16 utfs;		/* UCC transmit FIFO size */
	u8 res4[0x2];
	u16 utfet;		/* UCC transmit FIFO emergency threshold */
	u8 res5[0x2];
	u16 utftt;		/* UCC transmit FIFO transmit threshold */
	u8 res6[0x2];
	u16 utpt;		/* UCC transmit polling timer */
	u8 res7[0x2];
	u32 urtry;		/* UCC retry counter register */
	u8 res8[0x4C];
	u8 guemr;		/* UCC general extended mode register */
	u8 res9[0x100 - 0x091];
	uec_t ucc_eth;
} __attribute__ ((packed)) ucc_fast_t;

/* QE UCC
*/
typedef struct ucc_common {
	u8 res1[0x90];
	u8 guemr;
	u8 res2[0x200 - 0x091];
} __attribute__ ((packed)) ucc_common_t;

typedef struct ucc {
	union {
		ucc_slow_t slow;
		ucc_fast_t fast;
		ucc_common_t common;
	};
} __attribute__ ((packed)) ucc_t;

/* MultiPHY UTOPIA POS Controllers (UPC)
*/
typedef struct upc {
	u32 upgcr;		/* UTOPIA/POS general configuration register */
	u32 uplpa;		/* UTOPIA/POS last PHY address */
	u32 uphec;		/* ATM HEC register */
	u32 upuc;		/* UTOPIA/POS UCC configuration */
	u32 updc1;		/* UTOPIA/POS device 1 configuration */
	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
	u32 updc3;		/* UTOPIA/POS device 3 configuration */
	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
	u8 res0[0xC];
	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
	u32 upde1;		/* UTOPIA/POS device 1 event */
	u32 upde2;		/* UTOPIA/POS device 2 event */
	u32 upde3;		/* UTOPIA/POS device 3 event */
	u32 upde4;		/* UTOPIA/POS device 4 event */
	u16 uprp1;
	u16 uprp2;
	u16 uprp3;
	u16 uprp4;
	u8 res1[0x8];
	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
	u32 uper1;		/* Device 1 port enable register */
	u32 uper2;		/* Device 2 port enable register */
	u32 uper3;		/* Device 3 port enable register */
	u32 uper4;		/* Device 4 port enable register */
	u8 res2[0x150];
} __attribute__ ((packed)) upc_t;

/* SDMA
*/
typedef struct sdma {
	u32 sdsr;		/* Serial DMA status register */
	u32 sdmr;		/* Serial DMA mode register */
	u32 sdtr1;		/* SDMA system bus threshold register */
	u32 sdtr2;		/* SDMA secondary bus threshold register */
	u32 sdhy1;		/* SDMA system bus hysteresis register */
	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
	u32 sdta1;		/* SDMA system bus address register */
	u32 sdta2;		/* SDMA secondary bus address register */
	u32 sdtm1;		/* SDMA system bus MSNUM register */
	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
	u8 res0[0x10];
	u32 sdaqr;		/* SDMA address bus qualify register */
	u32 sdaqmr;		/* SDMA address bus qualify mask register */
	u8 res1[0x4];
	u32 sdwbcr;		/* SDMA CAM entries base register */
	u8 res2[0x38];
} __attribute__ ((packed)) sdma_t;

/* Debug Space
*/
typedef struct dbg {
	u32 bpdcr;		/* Breakpoint debug command register */
	u32 bpdsr;		/* Breakpoint debug status register */
	u32 bpdmr;		/* Breakpoint debug mask register */
	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
	u8 res0[0x8];
	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
	u8 res1[0x8];
	u32 bprmir;		/* Breakpoint request mode immediate register */
	u32 bprmsr;		/* Breakpoint request mode serial register */
	u32 bpemr;		/* Breakpoint exit mode register */
	u8 res2[0x48];
} __attribute__ ((packed)) dbg_t;

/* RISC Special Registers (Trap and Breakpoint)
*/
typedef struct rsp {
	u8 fixme[0x100];
} __attribute__ ((packed)) rsp_t;

typedef struct qe_immap {
	qe_iram_t iram;		/* I-RAM */
	qe_ic_t ic;		/* Interrupt Controller */
	cp_qe_t cp;		/* Communications Processor */
	qe_mux_t qmx;		/* QE Multiplexer */
	qe_timers_t qet;	/* QE Timers */
	spi_t spi[0x2];		/* spi  */
	mcc_t mcc;		/* mcc */
	qe_brg_t brg;		/* brg */
	usb_t usb;		/* USB */
	si1_t si1;		/* SI */
	u8 res11[0x800];
	sir_t sir;		/* SI Routing Tables  */
	ucc_t ucc1;		/* ucc1 */
	ucc_t ucc3;		/* ucc3 */
	ucc_t ucc5;		/* ucc5 */
	ucc_t ucc7;		/* ucc7 */
	u8 res12[0x600];
	upc_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
	ucc_t ucc2;		/* ucc2 */
	ucc_t ucc4;		/* ucc4 */
	ucc_t ucc6;		/* ucc6 */
	ucc_t ucc8;		/* ucc8 */
	u8 res13[0x600];
	upc_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
	sdma_t sdma;		/* SDMA */
	dbg_t dbg;		/* Debug Space */
	rsp_t rsp[0x2];		/* RISC Special Registers
				 * (Trap and Breakpoint) */
	u8 res14[0x300];
	u8 res15[0x3A00];
	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
#if defined(CONFIG_MPC8568)
	u8 muram[0x10000];	/* 0x1_0000 -  0x2_0000 Multi-user RAM */
	u8 res17[0x20000];	/* 0x2_0000 -  0x4_0000 */
#else
	u8 muram[0xC000];	/* 0x110000 -  0x11C000 Multi-user RAM */
	u8 res17[0x24000];	/* 0x11C000 -  0x140000 */
	u8 res18[0xC0000];	/* 0x140000 -  0x200000 */
#endif
} __attribute__ ((packed)) qe_map_t;

extern qe_map_t *qe_immr;

#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE		0x10000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE		0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE		0x4000UL
#endif

#endif				/* __IMMAP_QE_H__ */