immap_qe.h

u-boot1.3德国DENX小组开发的用于多种嵌入式CPU的bootloader

/*
 * QUICC Engine (QE) Internal Memory Map.
 * The Internal Memory Map for devices with QE on them. This
 * is the superset of all QE devices (8360, etc.).
 *
 * Copyright (c) 2006 Freescale Semiconductor, Inc.
 * Author: Shlomi Gridih <[e-mail]>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __IMMAP_QE_H__
#define __IMMAP_QE_H__

/* QE I-RAM
*/
typedef struct qe_iram {
	u32 iadd;		/* I-RAM Address Register */
	u32 idata;		/* I-RAM Data Register    */
	u8 res0[0x78];
} __attribute__ ((packed)) qe_iram_t;

/* QE Interrupt Controller
*/
typedef struct qe_ic {
	u32 qicr;
	u32 qivec;
	u32 qripnr;
	u32 qipnr;
	u32 qipxcc;
	u32 qipycc;
	u32 qipwcc;
	u32 qipzcc;
	u32 qimr;
	u32 qrimr;
	u32 qicnr;
	u8 res0[0x4];
	u32 qiprta;
	u32 qiprtb;
	u8 res1[0x4];
	u32 qricr;
	u8 res2[0x20];
	u32 qhivec;
	u8 res3[0x1C];
} __attribute__ ((packed)) qe_ic_t;

/* Communications Processor
*/
typedef struct cp_qe {
	u32 cecr;		/* QE command register */
	u32 ceccr;		/* QE controller configuration register */
	u32 cecdr;		/* QE command data register */
	u8 res0[0xA];
	u16 ceter;		/* QE timer event register */
	u8 res1[0x2];
	u16 cetmr;		/* QE timers mask register */
	u32 cetscr;		/* QE time-stamp timer control register */
	u32 cetsr1;		/* QE time-stamp register 1 */
	u32 cetsr2;		/* QE time-stamp register 2 */
	u8 res2[0x8];
	u32 cevter;		/* QE virtual tasks event register */
	u32 cevtmr;		/* QE virtual tasks mask register */
	u16 cercr;		/* QE RAM control register */
	u8 res3[0x2];
	u8 res4[0x24];
	u16 ceexe1;		/* QE external request 1 event register */
	u8 res5[0x2];
	u16 ceexm1;		/* QE external request 1 mask register */
	u8 res6[0x2];
	u16 ceexe2;		/* QE external request 2 event register */
	u8 res7[0x2];
	u16 ceexm2;		/* QE external request 2 mask register */
	u8 res8[0x2];
	u16 ceexe3;		/* QE external request 3 event register */
	u8 res9[0x2];
	u16 ceexm3;		/* QE external request 3 mask register */
	u8 res10[0x2];
	u16 ceexe4;		/* QE external request 4 event register */
	u8 res11[0x2];
	u16 ceexm4;		/* QE external request 4 mask register */
	u8 res12[0x2];
	u8 res13[0x280];
} __attribute__ ((packed)) cp_qe_t;

/* QE Multiplexer
*/
typedef struct qe_mux {
	u32 cmxgcr;		/* CMX general clock route register    */
	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
	u32 cmxupcr;		/* CMX UPC clock route register        */
	u8 res0[0x1C];
} __attribute__ ((packed)) qe_mux_t;

/* QE Timers
*/
typedef struct qe_timers {
	u8 gtcfr1;		/* Timer 1 2 global configuration register */
	u8 res0[0x3];
	u8 gtcfr2;		/* Timer 3 4 global configuration register */
	u8 res1[0xB];
	u16 gtmdr1;		/* Timer 1 mode register */
	u16 gtmdr2;		/* Timer 2 mode register */
	u16 gtrfr1;		/* Timer 1 reference register */
	u16 gtrfr2;		/* Timer 2 reference register */
	u16 gtcpr1;		/* Timer 1 capture register */
	u16 gtcpr2;		/* Timer 2 capture register */
	u16 gtcnr1;		/* Timer 1 counter */
	u16 gtcnr2;		/* Timer 2 counter */
	u16 gtmdr3;		/* Timer 3 mode register */
	u16 gtmdr4;		/* Timer 4 mode register */
	u16 gtrfr3;		/* Timer 3 reference register */
	u16 gtrfr4;		/* Timer 4 reference register */
	u16 gtcpr3;		/* Timer 3 capture register */
	u16 gtcpr4;		/* Timer 4 capture register */
	u16 gtcnr3;		/* Timer 3 counter */
	u16 gtcnr4;		/* Timer 4 counter */
	u16 gtevr1;		/* Timer 1 event register */
	u16 gtevr2;		/* Timer 2 event register */
	u16 gtevr3;		/* Timer 3 event register */
	u16 gtevr4;		/* Timer 4 event register */
	u16 gtps;		/* Timer 1 prescale register */
	u8 res2[0x46];
} __attribute__ ((packed)) qe_timers_t;

/* BRG
*/
typedef struct qe_brg {
	u32 brgc1;		/* BRG1 configuration register  */
	u32 brgc2;		/* BRG2 configuration register  */
	u32 brgc3;		/* BRG3 configuration register  */
	u32 brgc4;		/* BRG4 configuration register  */
	u32 brgc5;		/* BRG5 configuration register  */
	u32 brgc6;		/* BRG6 configuration register  */
	u32 brgc7;		/* BRG7 configuration register  */
	u32 brgc8;		/* BRG8 configuration register  */
	u32 brgc9;		/* BRG9 configuration register  */
	u32 brgc10;		/* BRG10 configuration register */
	u32 brgc11;		/* BRG11 configuration register */
	u32 brgc12;		/* BRG12 configuration register */
	u32 brgc13;		/* BRG13 configuration register */
	u32 brgc14;		/* BRG14 configuration register */
	u32 brgc15;		/* BRG15 configuration register */
	u32 brgc16;		/* BRG16 configuration register */
	u8 res0[0x40];
} __attribute__ ((packed)) qe_brg_t;

/* SPI
*/
typedef struct spi {
	u8 res0[0x20];
	u32 spmode;		/* SPI mode register */
	u8 res1[0x2];
	u8 spie;		/* SPI event register */
	u8 res2[0x1];
	u8 res3[0x2];
	u8 spim;		/* SPI mask register */
	u8 res4[0x1];
	u8 res5[0x1];
	u8 spcom;		/* SPI command register  */
	u8 res6[0x2];
	u32 spitd;		/* SPI transmit data register (cpu mode) */
	u32 spird;		/* SPI receive data register (cpu mode) */
	u8 res7[0x8];
} __attribute__ ((packed)) spi_t;

/* SI
*/
typedef struct si1 {
	u16 siamr1;		/* SI1 TDMA mode register */
	u16 sibmr1;		/* SI1 TDMB mode register */
	u16 sicmr1;		/* SI1 TDMC mode register */
	u16 sidmr1;		/* SI1 TDMD mode register */
	u8 siglmr1_h;		/* SI1 global mode register high */
	u8 res0[0x1];
	u8 sicmdr1_h;		/* SI1 command register high */
	u8 res2[0x1];
	u8 sistr1_h;		/* SI1 status register high */
	u8 res3[0x1];
	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
	u8 res4[0x8];
	u16 siemr1;		/* SI1 TDME mode register 16 bits */
	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
	u8 res5[0x1];
	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
	u8 res6[0x1];
	u8 sistr1_l;		/* SI1 status register low 8 bits */
	u8 res7[0x1];
	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
	u8 res8[0x8];
	u32 siml1;		/* SI1 multiframe limit register */
	u8 siedm1;		/* SI1 extended diagnostic mode register */
	u8 res9[0xBB];
} __attribute__ ((packed)) si1_t;

/* SI Routing Tables
*/
typedef struct sir {
	u8 tx[0x400];
	u8 rx[0x400];
	u8 res0[0x800];
} __attribute__ ((packed)) sir_t;

/* USB Controller.
*/
typedef struct usb_ctlr {
	u8 usb_usmod;
	u8 usb_usadr;
	u8 usb_uscom;
	u8 res1[1];
	u16 usb_usep1;
	u16 usb_usep2;
	u16 usb_usep3;
	u16 usb_usep4;
	u8 res2[4];
	u16 usb_usber;
	u8 res3[2];
	u16 usb_usbmr;
	u8 res4[1];
	u8 usb_usbs;
	u16 usb_ussft;
	u8 res5[2];
	u16 usb_usfrn;
	u8 res6[0x22];
} __attribute__ ((packed)) usb_t;

/* MCC
*/
typedef struct mcc {
	u32 mcce;		/* MCC event register */
	u32 mccm;		/* MCC mask register */
	u32 mccf;		/* MCC configuration register */
	u32 merl;		/* MCC emergency request level register */
	u8 res0[0xF0];
} __attribute__ ((packed)) mcc_t;

/* QE UCC Slow
*/
typedef struct ucc_slow {
	u32 gumr_l;		/* UCCx general mode register (low) */
	u32 gumr_h;		/* UCCx general mode register (high) */
	u16 upsmr;		/* UCCx protocol-specific mode register */
	u8 res0[0x2];
	u16 utodr;		/* UCCx transmit on demand register */
	u16 udsr;		/* UCCx data synchronization register */
	u16 ucce;		/* UCCx event register */
	u8 res1[0x2];
	u16 uccm;		/* UCCx mask register */
	u8 res2[0x1];
	u8 uccs;		/* UCCx status register */
	u8 res3[0x24];
	u16 utpt;
	u8 guemr;		/* UCC general extended mode register */
	u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;

typedef struct ucc_mii_mng {
	u32 miimcfg;		/* MII management configuration reg    */
	u32 miimcom;		/* MII management command reg          */
	u32 miimadd;		/* MII management address reg          */
	u32 miimcon;		/* MII management control reg          */