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📄 mpc8548cds.h

📁 u-boot1.3德国DENX小组开发的用于多种嵌入式CPU的bootloader
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#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */#define CONFIG_HARD_I2C		/* I2C with hardware support*/#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */#define CFG_I2C_EEPROM_ADDR	0x57#define CFG_I2C_SLAVE		0x7F#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */#define CFG_I2C_OFFSET		0x3000/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */#define CFG_PCI1_MEM_BASE	0x80000000#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */#define CFG_PCI1_IO_BASE	0x00000000#define CFG_PCI1_IO_PHYS	0xe2000000#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */#ifdef CONFIG_PCI2#define CFG_PCI2_MEM_BASE	0xa0000000#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */#define CFG_PCI2_IO_BASE	0x00000000#define CFG_PCI2_IO_PHYS	0xe2800000#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */#endif#ifdef CONFIG_PCIE1#define CFG_PCIE1_MEM_BASE	0xa0000000#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */#define CFG_PCIE1_IO_BASE	0x00000000#define CFG_PCIE1_IO_PHYS	0xe3000000#define CFG_PCIE1_IO_SIZE	0x00100000	/*   1M */#endif#ifdef CONFIG_RIO/* * RapidIO MMU */#define CFG_RIO_MEM_BASE	0xC0000000#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M */#endif#ifdef CONFIG_LEGACY#define BRIDGE_ID 17#define VIA_ID 2#else#define BRIDGE_ID 28#define VIA_ID 4#endif#if defined(CONFIG_PCI)#define CONFIG_NET_MULTI#define CONFIG_PCI_PNP			/* do pci plug-and-play */#undef CONFIG_EEPRO100#undef CONFIG_TULIP#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup *//* PCI view of System Memory */#define CFG_PCI_MEMORY_BUS	0x00000000#define CFG_PCI_MEMORY_PHYS	0x00000000#define CFG_PCI_MEMORY_SIZE	0x80000000#endif	/* CONFIG_PCI */#if defined(CONFIG_TSEC_ENET)#ifndef CONFIG_NET_MULTI#define CONFIG_NET_MULTI	1#endif#define CONFIG_MII		1	/* MII PHY management */#define CONFIG_TSEC1	1#define CONFIG_TSEC1_NAME	"eTSEC0"#define CONFIG_TSEC2	1#define CONFIG_TSEC2_NAME	"eTSEC1"#define CONFIG_TSEC3	1#define CONFIG_TSEC3_NAME	"eTSEC2"#define CONFIG_TSEC4#define CONFIG_TSEC4_NAME	"eTSEC3"#undef CONFIG_MPC85XX_FEC#define TSEC1_PHY_ADDR		0#define TSEC2_PHY_ADDR		1#define TSEC3_PHY_ADDR		2#define TSEC4_PHY_ADDR		3#define TSEC1_PHYIDX		0#define TSEC2_PHYIDX		0#define TSEC3_PHYIDX		0#define TSEC4_PHYIDX		0#define TSEC1_FLAGS		TSEC_GIGABIT#define TSEC2_FLAGS		TSEC_GIGABIT#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)/* Options are: eTSEC[0-3] */#define CONFIG_ETHPRIME		"eTSEC0"#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */#endif	/* CONFIG_TSEC_ENET *//* * Environment */#define CFG_ENV_IS_IN_FLASH	1#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */#define CFG_ENV_SIZE		0x2000#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change *//* * BOOTP options */#define CONFIG_BOOTP_BOOTFILESIZE#define CONFIG_BOOTP_BOOTPATH#define CONFIG_BOOTP_GATEWAY#define CONFIG_BOOTP_HOSTNAME/* * Command line configuration. */#include <config_cmd_default.h>#define CONFIG_CMD_PING#define CONFIG_CMD_I2C#define CONFIG_CMD_MII#if defined(CONFIG_PCI)    #define CONFIG_CMD_PCI#endif#undef CONFIG_WATCHDOG			/* watchdog disabled *//* * Miscellaneous configurable options */#define CFG_LONGHELP			/* undef to save memory	*/#define CFG_LOAD_ADDR	0x2000000	/* default load address */#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */#if defined(CONFIG_CMD_KGDB)#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */#else#define CFG_CBSIZE	256		/* Console I/O Buffer Size */#endif#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS	16		/* max number of command args */#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */#define CFG_HZ		1000		/* decrementer freq: 1ms ticks *//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*//* Cache Configuration */#define CFG_DCACHE_SIZE	32768#define CFG_CACHELINE_SIZE	32#if defined(CONFIG_CMD_KGDB)#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/#endif/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */#define BOOTFLAG_WARM	0x02		/* Software reboot */#if defined(CONFIG_CMD_KGDB)#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */#endif/* * Environment Configuration *//* The mac addresses for all ethernet interface */#if defined(CONFIG_TSEC_ENET)#define CONFIG_HAS_ETH0#define CONFIG_ETHADDR	 00:E0:0C:00:00:FD#define CONFIG_HAS_ETH1#define CONFIG_ETH1ADDR	 00:E0:0C:00:01:FD#define CONFIG_HAS_ETH2#define CONFIG_ETH2ADDR	 00:E0:0C:00:02:FD#define CONFIG_HAS_ETH3#define CONFIG_ETH3ADDR	 00:E0:0C:00:03:FD#endif#define CONFIG_IPADDR	 192.168.1.253#define CONFIG_HOSTNAME	 unknown#define CONFIG_ROOTPATH	 /nfsroot#define CONFIG_BOOTFILE	8548cds/uImage.uboot#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */#define CONFIG_SERVERIP	 192.168.1.1#define CONFIG_GATEWAYIP 192.168.1.1#define CONFIG_NETMASK	 255.255.255.0#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/#define CONFIG_BAUDRATE	115200#if defined(CONFIG_PCIE1)#define PCIE_ENV \ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \	"pci d $b.0 130 1\0" \ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ "pcie1regs=setenv a e000a; run pciereg\0" \ "pcie1cfg=setenv b 3; run pciecfg\0" \ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"#else#define	PCIE_ENV ""#endif#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)#define PCI_ENV \ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \	"echo e;md ${a}e00 9\0" \ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \	"pci d.w $b.0 56 1\0" \ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"#else#define	PCI_ENV ""#endif#if defined(CONFIG_PCI1)#define PCI_ENV1 \ "pci1regs=setenv a e0008; run pcireg\0" \ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"#else#define	PCI_ENV1 ""#endif#if defined(CONFIG_PCI2)#define PCI_ENV2 \ "pci2regs=setenv a e0009; run pcireg\0" \ "pci2err=setenv a e0009; setenv b 123; run pcierr\0"	\ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"#else#define	PCI_ENV2 ""#endif#if defined(CONFIG_TSEC_ENET)#define ENET_ENV \ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \	"md ${a}098 2\0" \ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \	"echo mib;md ${a}680 31\0" \ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ "enet1regs=setenv a e0024; run enetreg\0" \ "enet2regs=setenv a e0025; run enetreg\0" \ "enet3regs=setenv a e0026; run enetreg\0" \ "enet4regs=setenv a e0027; run enetreg\0"#else#define ENET_ENV ""#endif#define	CONFIG_EXTRA_ENV_SETTINGS				\ "netdev=eth0\0"						\ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\ "tftpflash=tftpboot $loadaddr $uboot; "			\	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\ "consoledev=ttyS1\0"				\ "ramdiskaddr=2000000\0"			\ "ramdiskfile=ramdisk.uboot\0"			\ "fdtaddr=c00000\0"				\ "fdtfile=mpc8548cds.dtb\0"			\ "eoi=mw e00400b0 0\0"				\ "iack=md e00400a0 1\0"				\ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \	"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ "ddrregs=setenv a e0002; run ddrreg\0"		\ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \	"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0"	\ "guregs=setenv a e00e0; run gureg\0"		\ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ "ecmregs=setenv a e0001; run ecmreg\0" \ "lawregs=md e0000c08 4b\0" \ "lbcregs=md e0005000 36\0" \ "dma0regs=md e0021100 12\0" \ "dma1regs=md e0021180 12\0" \ "dma2regs=md e0021200 12\0" \ "dma3regs=md e0021280 12\0" \ PCIE_ENV \ PCI_ENV \ PCI_ENV1 \ PCI_ENV2 \ ENET_ENV#define CONFIG_NFSBOOTCOMMAND						\   "setenv bootargs root=/dev/nfs rw "					\      "nfsroot=$serverip:$rootpath "					\      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \      "console=$consoledev,$baudrate $othbootargs;"			\   "tftp $loadaddr $bootfile;"						\   "tftp $fdtaddr $fdtfile;"						\   "bootm $loadaddr - $fdtaddr"#define CONFIG_RAMBOOTCOMMAND \   "setenv bootargs root=/dev/ram rw "					\      "console=$consoledev,$baudrate $othbootargs;"			\   "tftp $ramdiskaddr $ramdiskfile;"					\   "tftp $loadaddr $bootfile;"						\   "tftp $fdtaddr $fdtfile;"						\   "bootm $loadaddr $ramdiskaddr $fdtaddr"#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND#endif	/* __CONFIG_H */

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