fir_rtl.vhd

Simple fir digital filter

--------------------------------------------------------------------------------
-- Description : This is a fir filter design unit for testpurposes only
-- References  : 
--------------------------------------------------------------------------------
-- Author      : Kurt Illmayer (IL) 
-- Department  : Bulme Graz Goesting 
-- Created     : 
-- Last update : 2005/06/29
-- Language    : vhdl '87 
--------------------------------------------------------------------------------
-- Revisions   : 
-- Date         Version   Author   Description 
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fir is
  port( -- System clock
        clock_i           : in  std_ulogic;
        -- active low reset
        reset_ni          : in  std_ulogic;
        -- output a for the seven segment display
        data_i            : in  std_ulogic_vector(7 downto 0);
        -- output b for the seven segment display
        data_o            : out std_ulogic_vector(7 downto 0));
end fir;

architecture rtl of fir is

 signal data_1          : std_logic_vector(7 downto 0);

 signal data_2          : std_logic_vector(7 downto 0);

 signal data_3          : std_logic_vector(7 downto 0);
 
 signal multiply_data_0 : std_logic_vector(15 downto 0);
 
 signal multiply_data_1 : std_logic_vector(15 downto 0);
 
 signal multiply_data_2 : std_logic_vector(15 downto 0);
 
 signal multiply_data_3 : std_logic_vector(15 downto 0);
 
 constant coeff_data_0  : std_logic_vector(7 downto 0):="11111111";
 
 constant coeff_data_1  : std_logic_vector(7 downto 0):="11111111";
 
 constant coeff_data_2  : std_logic_vector(7 downto 0):="11111111";
 
 constant coeff_data_3  : std_logic_vector(7 downto 0):="11111111";

 signal  adder_data     : std_logic_vector(7 downto 0);

begin

   shiftreg: process (clock_i, reset_ni)
	
   begin
      
      if (reset_ni = '0') then

	 data_1(7 downto 0) <= (others =>'0');
	  
  	 data_2(7 downto 0) <= (others =>'0');

	 data_3(7 downto 0) <= (others =>'0');
			  
      elsif (clock_i'event and clock_i ='1') then

         data_1(7 downto 0) <= to_stdlogicvector(data_i(7 downto 0));

         data_2(7 downto 0) <= data_1(7 downto 0);

         data_3(7 downto 0) <= data_2(7 downto 0);

      end if;

   end process shiftreg;
	
	
   Multiplier: process(clock_i, reset_ni)

   begin

     if (reset_ni = '0') then

	 multiply_data_0(15 downto 0) <= (others =>'0');

	 multiply_data_1(15 downto 0) <= (others =>'0');
					 
	 multiply_data_2(15 downto 0) <= (others =>'0');

	 multiply_data_3(15 downto 0) <= (others =>'0');

     elsif (clock_i'event and clock_i ='1') then

         multiply_data_0(15 downto 0) <= unsigned(coeff_data_0(7 downto 0)) * unsigned(data_i(7 downto 0));
		
	 multiply_data_1(15 downto 0) <= unsigned(coeff_data_1(7 downto 0)) * unsigned(data_1(7 downto 0));
		
	 multiply_data_2(15 downto 0) <= unsigned(coeff_data_2(7 downto 0)) * unsigned(data_2(7 downto 0));
		
	 multiply_data_3(15 downto 0) <= unsigned(coeff_data_3(7 downto 0)) * unsigned(data_3(7 downto 0));
		
     end if;
	   
   end process Multiplier;
    
	 
   Adder: process(clock_i, reset_ni)

   begin  

      if (reset_ni = '0') then

       	 adder_data(7 downto 0) <= (others =>'0');

      elsif (clock_i'event and clock_i ='1') then

         adder_data(7 downto 0) <=  multiply_data_0(15 downto 8) + multiply_data_1(15 downto 8)
                                  + multiply_data_2(15 downto 8) + multiply_data_3(15 downto 8);    
      end if;
	   
   end process Adder;	 
	 
   data_o(7 downto 0) <= to_stdulogicvector(adder_data(7 downto 0));
		
end rtl;