lcd_control_rtl_v3.vhd

LCD display driver for xilinx fpga

------------------------------------------------------------------------
--  : LCD Information :
--  -----------------------------------------------------------------
--  : Function Set :                  "0 0 1 DL | N F x x",        40 祍
--  : DL = Interface width. 1: 8-bit,  0: 4-bit      (default is 8-bit)
--  : N  = Display lines    1: 2-line, 0: 1-line     (default is 1-line)
--  : F  = Font type        1: 5x11,   0: 5x8        (default is 5x8)
--  -----------------------------------------------------------------
--  : Cursor and Shift control :      "0 0 0 1 | S/C R/L * *",     40 祍
--  : S/C= Shift Cursor     1: Display shift, 0: Cursor move
--  : R/L= Shift Right/left 1: Shift to the right, 0: shift to the left
--  -----------------------------------------------------------------
--  : Display Control :               "0 0 0 0 | 1 D C B",         40 祍
--  : D  = Display on/off   1: on, 0: off            (default is off)
--  : C  = Cursor on/off    1: on, 0: off            (default is off)
--  : B  = Blinking on/off  1: on, 0: off            (default is off)
--  -----------------------------------------------------------------
 --  : Entry Mode :                    "0 0 0 0 | 0 1 I/D S",       40 祍
--  : I/D= Increment Addr   1: inc by 1, 0: dec by 1 (default is inc by 1)
--  : S  = Display shift    1: on, 0: off            (default is off)
--  -----------------------------------------------------------------
--  : Return Home :                   "0 0 0 0 | 0 0 1 *",          1.64 ms
--  -----------------------------------------------------------------
--  : Clear Display :                 "0 0 0 0 | 0 0 0 1",          1.64 ms
--  -----------------------------------------------------------------
--  : Set DDRAM address :             "1 A6 A5 A4 | A3 A2 A1 A0",  40 祍
--  -----------------------------------------------------------------
--  : Set CGRAM address :             "0  1 A5 A4 | A3 A2 A1 A0",  40 祍
--  -----------------------------------------------------------------
--  : Write Data to CGRAM or DDRAM :  "D7 D6 D5 D4 | D3 D2 D1 D0", 40 祍
--  : LCD_rs_o = 1;
--  -----------------------------------------------------------------
--  : Read Data from CGRAM or DDRAM : "D7 D6 D5 D4 | D3 D2 D1 D0", 40 祍
--  : LCD_rs_o = 1;
--  -----------------------------------------------------------------
--  : Read Busy flag and address:     "BF A6 A5 A4 | A3 A2 A1 A0",  1 祍
--  -----------------------------------------------------------------
--  : Character Display addresses :
--  :	16x2 module is two lines by 16 chars 
--  -----------------------------------------------------------------
--  : Line 1 addresses are 00h to 0Fh  ( 0 to 15)
--  : Line 2 addresses are 40h to 4Fh  (64 to 79)
--            
--   -----------------------------------------------
--  |00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f|
--  |40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f|
--   -----------------------------------------------
--
--  -----------------------------------------------------------------
--
--  : Time :
--
--               1*1   = 1      clock cycles (20 ns) =  20 ns  
--               2*1   = 2      clock cycles (20 ns) =  40 ns
--              12*1   = 12     clock cycles (20 ns) = 240 ns
--              50*1   = 50     clock cycles (20 ns) =   1 祍
--              50*40  = 2000   clock cycles (20 ns) =  40 祍
--            5000*1   = 5000   clock cycles (20 ns) = 100 祍
--           82000*1   = 82000  clock cycles (20 ns) =   1.64 ms
--          205000*1   = 205000 clock cycles (20 ns) =   4.1 ms
--          750000*1   = 750000 clock cycles (20 ns) =  15 ms
--
--          t_hold_c          =      1   clock cycles (20 ns) =  20 ns
--          t_setup_c         =      2   clock cycles (20 ns) =  40 ns 
--          t_pulse_c         =     12   clock cycles (20 ns) = 240 ns
--          t_upper_lower_c   =     50   clock cycles (20 ns) =   1 祍
--          t_next_pulse_c    =   2000   clock cycles (20 ns) =  40 祍
--          t_wait_c          =   5000   clock cycles (20 ns) = 100 祍
--          t_clear_display_c =  82000   clock cycles (20 ns) =   1.64 ms
--          t_begin_c         = 205000   clock cycles (20 ns) =   4.1 ms
--          t_power_up_c      = 750000   clock cycles (20 ns) =  15 ms
--  -------------------------------------------------------------------
--
--            : DATA WRITE: 
--              ______ _____________________________ ____________
--          RS  ______X_________valid_RS_level______X____________
--                    |                             |
--	              |                             |
--                    |                             |
--                  ->|t_setup_c|<-  t_hold_c->|    |<--
--              ______|         |              |    |_____________
--          R/W       \_________|______________|____/
--                              |              |
--                              |              |
--                              |              |
--                              |<-------------|----t_pulse_c---->|
--                              |______________|                  |_________
--          E   ________________/              \__________________/
--                   t_rise_c-->||<--       -->||<--t_fall_c
--                                             ||
--                  t_data_setup_c->|          |<--
--                                  |        -->|   |<--t_data_hold_c
--                __________________|_______________|________________
--          D0-D7 __________________X__valid_data___X________________
--
--
--  -----------------------------------------------------------------
--
--            : DATA READ : 
--              ______ _____________________________ ________________
--          RS  ______X_________valid_RS_level______X________________
--                    |                             |
--                    |                             |
--                  ->|t_setup_c|<-  t_hold_c->|    |<--
--                    |_________|______________|____|
--          R/W ______/         |              |    \_____________
--                              |              |
--                              |              |
--                              |              |
--                              |<-------------|----t_pulse_c---->|
--                              |______________|                  |_________
--          E   ________________/              \__________________/
--                   t_rise_c-->||<--       -->||<--t_fall_c
--                              |               |
--                 t_data_setup_c-->|   |<--        |
--                                  |        -->|   |<--t_data_holc_c
--               ___________________|_______________|________________
--          data ___________________X__valid_data___X_______________
--
--
--  -----------------------------------------------------------------------------
--
--                   ;ASCII table
--                   ;
--                   CONSTANT character_a, 61
--                   CONSTANT character_b, 62
--                   CONSTANT character_c, 63
--                   CONSTANT character_d, 64
--                   CONSTANT character_e, 65
--                   CONSTANT character_f, 66
--                   CONSTANT character_g, 67
--                   CONSTANT character_h, 68
--                   CONSTANT character_i, 69
--                   CONSTANT character_j, 6A
--                   CONSTANT character_k, 6B
--                   CONSTANT character_l, 6C
--                   CONSTANT character_m, 6D
--                   CONSTANT character_n, 6E
--                   CONSTANT character_o, 6F
--                   CONSTANT character_p, 70
--                   CONSTANT character_q, 71
--                   CONSTANT character_r, 72
--                   CONSTANT character_s, 73
--                   CONSTANT character_t, 74
--                   CONSTANT character_u, 75
--                   CONSTANT character_v, 76
--                   CONSTANT character_w, 77
--                   CONSTANT character_x, 78
--                   CONSTANT character_y, 79
--                   CONSTANT character_z, 7A
--                   CONSTANT character_A, 41
--                   CONSTANT character_B, 42
--                   CONSTANT character_C, 43
--                   CONSTANT character_D, 44
--                   CONSTANT character_E, 45
--                   CONSTANT character_F, 46
--                   CONSTANT character_G, 47
--                   CONSTANT character_H, 48
--                   CONSTANT character_I, 49
--                   CONSTANT character_J, 4A
--                   CONSTANT character_K, 4B
--                   CONSTANT character_L, 4C
--                   CONSTANT character_M, 4D
--                   CONSTANT character_N, 4E
--                   CONSTANT character_O, 4F
--                   CONSTANT character_P, 50
--                   CONSTANT character_Q, 51
--                   CONSTANT character_R, 52
--                   CONSTANT character_S, 53
--                   CONSTANT character_T, 54
--                   CONSTANT character_U, 55
--                   CONSTANT character_V, 56
--                   CONSTANT character_W, 57
--                   CONSTANT character_X, 58
--                   CONSTANT character_Y, 59
--                   CONSTANT character_Z, 5A
--                   CONSTANT character_0, 30
--                   CONSTANT character_1, 31
--                   CONSTANT character_2, 32
--                   CONSTANT character_3, 33
--                   CONSTANT character_4, 34
--                   CONSTANT character_5, 35
--                   CONSTANT character_6, 36
--                   CONSTANT character_7, 37
--                   CONSTANT character_8, 38
--                   CONSTANT character_9, 39
--                   CONSTANT character_colon, 3A
--                   CONSTANT character_stop, 2E
--                   CONSTANT character_semi_colon, 3B   ;';'
--                   CONSTANT character_minus, 2D        ;'-'
--                   CONSTANT character_divide, 2F       ;'/'
--                   CONSTANT character_plus, 2B         ;'+'
--                   CONSTANT character_comma, 2C        ;','
--                   CONSTANT character_less_than, 3C    ;'<='
--                   CONSTANT character_greater_than, 3E ;'>='
--                   CONSTANT character_equals, 3D       ;'='
--                   CONSTANT character_space, 20
--                   CONSTANT character_CR, 0D           ;carriage return
--                   CONSTANT character_question, 3F     ;'?'
--                   CONSTANT character_dollar, 24       ;'$'
--                   CONSTANT character_exclaim, 21      ;'!'
--                   CONSTANT character_BS, 08           ;Back Space command character
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity lcd_control is
 port(-- System clock: 50 MHz
      clock_i    : in  std_ulogic;
      -- System reset
      reset_i    : in  std_ulogic;
      -- 4 bit lcd data signal
      lcd_data_o : out std_ulogic_vector(3 downto 0);
      -- lcd enable output signal
      lcd_e_o    : out std_ulogic;
      -- lcd register select output signal
      lcd_rs_o   : out std_ulogic;
      -- lcd read/ not write output signal
      lcd_rw_o   : out std_ulogic;
      -- strata flash chip enable output signal
      sf_ce0_o   : out std_ulogic);
end lcd_control;

architecture rtl of lcd_control is
  
  type     states   is (lcdreset,init1,init2,init3,init4,init5,init6,init7,init8,init9,
			init10,init11,init12,init13,init14,init15,init16,init17,init18,init19,
			init20,init21,init22,init23,init24,init25,init26,init27,init28,init29,
			init30,init31);
  signal   state_lcd           : states;
  signal   lcd_e               : std_ulogic;
  signal   lcd_rs              : std_ulogic;
  signal   lcd_data            : std_ulogic_vector(3 downto 0);
  signal   lcd_rw              : std_ulogic;
  constant t_hold_c            : integer range 0 to      1:=     1; --  20 ns
  constant t_setup_c           : integer range 0 to      2:=     2; --  40 ns
  constant t_pulse_c           : integer range 0 to     15:=    15; -- 300 ns
  constant t_upper_lower_c     : integer range 0 to     50:=    50; --   1 祍
  constant t_next_pulse_c      : integer range 0 to   2000:=  2000; --  40 祍
  constant t_wait_c            : integer range 0 to   5000:=  5000; -- 100 祍
  constant t_clear_display_c   : integer range 0 to 82000 := 82000; --   1.64 ms
  constant t_begin_c           : integer range 0 to 205000:=205000; --   4.1 ms
  constant t_power_up_c        : integer range 0 to 750000:=750000; --  15 ms
	   -- 8 bit interface
  constant function_set_8bit_c : std_ulogic_vector(7 downto 0):= x"33";
	   -- 8 bit interface, 4 bit interface
  constant function_set_4bit_c : std_ulogic_vector(7 downto 0):= x"32";
	   -- 4 bit interface, 2 lines, character 5x8 pixels font
  constant function_set_c      : std_ulogic_vector(7 downto 0):= x"28";  
	   -- address counter increment by 1, no shifting
  constant entry_mode_c        : std_ulogic_vector(7 downto 0):= x"06";
	   -- display on, no cursor, no blinking
  constant display_control_c   : std_ulogic_vector(7 downto 0):= x"0c";
	   -- clear all display information
  constant clear_display_c     : std_ulogic_vector(7 downto 0):= x"01"; 
	   -- set ddram start address Line 1
  constant set_ddram_address_c : std_ulogic_vector(7 downto 0):= x"80";
  	   -- set ddram start address Line 2
  constant set_ddram_address_c2: std_ulogic_vector(7 downto 0):= x"C0";
  constant data_1_c            : std_ulogic_vector(7 downto 0):= x"49";  --I
  constant data_2_c            : std_ulogic_vector(7 downto 0):= x"4C";  --L
  constant data_3_c            : std_ulogic_vector(7 downto 0):= x"4C";  --L
  constant data_4_c            : std_ulogic_vector(7 downto 0):= x"41";  --A
  constant data_5_c            : std_ulogic_vector(7 downto 0):= x"42";  --B
  constant data_6_c            : std_ulogic_vector(7 downto 0):= x"4F";  --O
  constant data_7_c            : std_ulogic_vector(7 downto 0):= x"52";  --R
  constant data_8_c            : std_ulogic_vector(7 downto 0):= x"20";  --Space
  signal   count               : integer range 0 to 750000;
  
begin

	lcd_e_o    <= lcd_e;
	
	lcd_rs_o   <= lcd_rs;

	lcd_rw_o   <= lcd_rw;

	sf_ce0_o   <= '1';

        lcd_data_o <= lcd_data;
	
	init_lcd : process (clock_i, reset_i) 

	begin

	  if(reset_i ='1') then

	    state_lcd  <= lcdreset;

	    count      <=  0;

	    lcd_e      <= '0';

	    lcd_rs     <= '1';

	    lcd_data   <= "0000";

            lcd_rw     <= '1';
	    
	  elsif (clock_i'event and clock_i = '1') then

	     case state_lcd is
				
	       when lcdreset => -- wait for 15 ms power up sequence

		 if(count = t_power_up_c) then

		   lcd_data  <= function_set_8bit_c(7 downto 4);
				  
		   lcd_rs    <= '0';  

		   lcd_e     <= '0';

                   lcd_rw    <= '0';
		   
		   count     <=  0;

		   state_lcd <= Init1;

		 else

		   count     <= count + 1;

		 end if;
		 
	       when init1 => -- wait for 4.1 ms

		 if(count = (t_begin_c + t_pulse_c)) then

                   lcd_data  <= function_set_8bit_c(3 downto 0);

                   lcd_rw    <= '0';
		   
		   state_lcd <= init2;

		   count     <= 0;

		 elsif (count = t_pulse_c) then
		   
                   lcd_rw    <= '1';

   		   count     <= count + 1;
		   
		 elsif (count = (t_pulse_c - t_hold_c)) then

		   lcd_e     <= '0';	

		   count     <= count + 1;
		   
		 elsif (count = t_setup_c) then

		   lcd_e     <= '1';   

		   count     <= count + 1;
		   
		 else

		   count     <= count + 1;

		 end if;

	       when init2 => -- wait for 100 祍

		 if(count = (t_pulse_c + t_wait_c)) then

                   lcd_data  <= function_set_4bit_c(7 downto 4);

                   lcd_rw    <= '0';
		   
		   state_lcd <= init3;

		   count     <= 0;
		   
		 elsif (count = t_pulse_c) then
		   
                   lcd_rw    <= '1';

   		   count     <= count + 1;
		   
		 elsif (count = (t_pulse_c - t_hold_c)) then
		   
		   lcd_e     <= '0';		   

		   count     <= count + 1;
		   
		 elsif (count = t_setup_c) then

		   lcd_e     <= '1';   

		   count     <= count + 1;
		   
		 else

		   count     <= count + 1;

		 end if;		 

	       when init3 => -- wait for 40 祍

		 if(count = (t_pulse_c + t_next_pulse_c)) then

                   lcd_data  <= function_set_4bit_c(3 downto 0);		   

                   lcd_rw    <= '0';
		   
		   state_lcd <= init4;
 
		   count     <= 0;
		   
		 elsif (count = t_pulse_c) then
		   
                   lcd_rw    <= '1';

   		   count     <= count + 1;		   
		   
		 elsif (count = (t_pulse_c - t_hold_c)) then
		   
		   lcd_e     <= '0';		   

		   count     <= count + 1;
		   
		 elsif (count = t_setup_c) then

		   lcd_e     <= '1';   

		   count     <= count + 1;
		   
		 else

		   count     <= count + 1;

		 end if;

	       when init4 => -- wait for 40 祍

		 if(count = (t_pulse_c + t_next_pulse_c)) then

                   lcd_data  <= function_set_c(7 downto 4);		   

                   lcd_rw    <= '0';
		   
		   state_lcd <= init5;

		   count     <= 0;
		   
		 elsif (count = t_pulse_c) then
		   
                   lcd_rw    <= '1';

   		   count     <= count + 1;
		   
		 elsif (count = (t_pulse_c - t_hold_c)) then
		   
		   lcd_e     <= '0';		   

		   count     <= count + 1;
		   
		 elsif (count = t_setup_c) then

		   lcd_e     <= '1';   

		   count     <= count + 1;
		   
		 else

		   count     <= count + 1;

		 end if;		 

	       when init5 => -- wait for 1 祍

		 if(count = (t_pulse_c + t_upper_lower_c)) then