time.fit.qmsg

24小时时钟设计程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 27 10:55:44 2008 " "Info: Processing started: Wed Feb 27 10:55:44 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off time -c time " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off time -c time" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "time EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"time\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "time.bdf" "" { Schematic "E:/Time/time.bdf" { { -648 -464 -296 -632 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fenpin:inst6\|7474:inst13\|10 Global clock " "Info: Automatically promoted signal \"fenpin:inst6\|7474:inst13\|10\" to use Global clock" {  } { { "7474.bdf" "" { Schematic "c:/program files/altera/quartus50/libraries/others/maxplus2/7474.bdf" { { 304 256 320 384 "10" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "hour:inst\|time4:inst2\|inst5 Global clock " "Info: Automatically promoted signal \"hour:inst\|time4:inst2\|inst5\" to use Global clock" {  } { { "time4.bdf" "" { Schematic "E:/Time/time4.bdf" { { 272 376 440 352 "inst5" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "minute:inst2\|time10:inst1\|inst8 Global clock " "Info: Automatically promoted signal \"minute:inst2\|time10:inst1\|inst8\" to use Global clock" {  } { { "time10.bdf" "" { Schematic "E:/Time/time10.bdf" { { 248 392 456 328 "inst8" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "minute:inst2\|time6:inst\|inst5 Global clock " "Info: Automatically promoted signal \"minute:inst2\|time6:inst\|inst5\" to use Global clock" {  } { { "time6.bdf" "" { Schematic "E:/Time/time6.bdf" { { 240 344 408 320 "inst5" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "second:inst1\|time10:inst1\|inst8 Global clock " "Info: Automatically promoted signal \"second:inst1\|time10:inst1\|inst8\" to use Global clock" {  } { { "time10.bdf" "" { Schematic "E:/Time/time10.bdf" { { 248 392 456 328 "inst8" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "second:inst1\|time6:inst\|inst5 Global clock " "Info: Automatically promoted signal \"second:inst1\|time6:inst\|inst5\" to use Global clock" {  } { { "time6.bdf" "" { Schematic "E:/Time/time6.bdf" { { 240 344 408 320 "inst5" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.889 ns register register " "Info: Estimated most critical path is register to register delay of 1.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:inst\|time2:inst1\|74161:inst\|f74161:sub\|87 1 REG LAB_X27_Y10 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y10; Fanout = 15; REG Node = 'hour:inst\|time2:inst1\|74161:inst\|f74161:sub\|87'" {  } { { "E:/Time/db/time_cmp.qrpt" "" { Report "E:/Time/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "E:/Time/db/time.quartus_db" { Floorplan "E:/Time/" "" "" { hour:inst|time2:inst1|74161:inst|f74161:sub|87 } "NODE_NAME" } "" } } { "f74161.bdf" "" { Schematic "c:/program files/altera/quartus50/libraries/others/maxplus2/f74161.bdf" { { 336 640 704 416 "87" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.114 ns) 0.740 ns hour:inst\|time4:inst2\|inst6~53 2 COMB LAB_X27_Y10 3 " "Info: 2: + IC(0.626 ns) + CELL(0.114 ns) = 0.740 ns; Loc. = LAB_X27_Y10; Fanout = 3; COMB Node = 'hour:inst\|time4:inst2\|inst6~53'" {  } { { "E:/Time/db/time_cmp.qrpt" "" { Report "E:/Time/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "E:/Time/db/time.quartus_db" { Floorplan "E:/Time/" "" "0.740 ns" { hour:inst|time2:inst1|74161:inst|f74161:sub|87 hour:inst|time4:inst2|inst6~53 } "NODE_NAME" } "" } } { "time4.bdf" "" { Schematic "E:/Time/time4.bdf" { { -16 136 200 32 "inst6" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.607 ns) 1.889 ns hour:inst\|time4:inst2\|74161:inst\|f74161:sub\|87 3 REG LAB_X27_Y10 12 " "Info: 3: + IC(0.542 ns) + CELL(0.607 ns) = 1.889 ns; Loc. = LAB_X27_Y10; Fanout = 12; REG Node = 'hour:inst\|time4:inst2\|74161:inst\|f74161:sub\|87'" {  } { { "E:/Time/db/time_cmp.qrpt" "" { Report "E:/Time/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "E:/Time/db/time.quartus_db" { Floorplan "E:/Time/" "" "1.149 ns" { hour:inst|time4:inst2|inst6~53 hour:inst|time4:inst2|74161:inst|f74161:sub|87 } "NODE_NAME" } "" } } { "f74161.bdf" "" { Schematic "c:/program files/altera/quartus50/libraries/others/maxplus2/f74161.bdf" { { 336 640 704 416 "87" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.721 ns 38.17 % " "Info: Total cell delay = 0.721 ns ( 38.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.168 ns 61.83 % " "Info: Total interconnect delay = 1.168 ns ( 61.83 % )" {  } {  } 0}  } { { "E:/Time/db/time_cmp.qrpt" "" { Report "E:/Time/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "E:/Time/db/time.quartus_db" { Floorplan "E:/Time/" "" "1.889 ns" { hour:inst|time2:inst1|74161:inst|f74161:sub|87 hour:inst|time4:inst2|inst6~53 hour:inst|time4:inst2|74161:inst|f74161:sub|87 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 27 10:55:49 2008 " "Info: Processing ended: Wed Feb 27 10:55:49 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}