hw1.tan.qmsg

一个模拟ISA界面的简易小程式

{ "Info" "ITDB_TH_RESULT" "PB\[15\]~reg0 SD\[15\] clk -2.394 ns register " "Info: th for register \"PB\[15\]~reg0\" (data pin = \"SD\[15\]\", clock pin = \"clk\") is -2.394 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.482 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 52 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.618 ns) 2.482 ns PB\[15\]~reg0 3 REG LCFF_X22_Y4_N29 1 " "Info: 3: + IC(0.667 ns) + CELL(0.618 ns) = 2.482 ns; Loc. = LCFF_X22_Y4_N29; Fanout = 1; REG Node = 'PB\[15\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { clk~clkctrl PB[15]~reg0 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.31 % ) " "Info: Total cell delay = 1.472 ns ( 59.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 40.69 % ) " "Info: Total interconnect delay = 1.010 ns ( 40.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { clk clk~clkctrl PB[15]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { clk {} clk~combout {} clk~clkctrl {} PB[15]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.025 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SD\[15\] 1 PIN PIN_AA12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AA12; Fanout = 1; PIN Node = 'SD\[15\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[15] } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.809 ns) 0.809 ns SD\[15\]~16 2 COMB IOC_X18_Y0_N1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = IOC_X18_Y0_N1; Fanout = 2; COMB Node = 'SD\[15\]~16'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.809 ns" { SD[15] SD[15]~16 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.008 ns) + CELL(0.053 ns) 4.870 ns PB\[15\]~reg0feeder 3 COMB LCCOMB_X22_Y4_N28 1 " "Info: 3: + IC(4.008 ns) + CELL(0.053 ns) = 4.870 ns; Loc. = LCCOMB_X22_Y4_N28; Fanout = 1; COMB Node = 'PB\[15\]~reg0feeder'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.061 ns" { SD[15]~16 PB[15]~reg0feeder } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.025 ns PB\[15\]~reg0 4 REG LCFF_X22_Y4_N29 1 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 5.025 ns; Loc. = LCFF_X22_Y4_N29; Fanout = 1; REG Node = 'PB\[15\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { PB[15]~reg0feeder PB[15]~reg0 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.017 ns ( 20.24 % ) " "Info: Total cell delay = 1.017 ns ( 20.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.008 ns ( 79.76 % ) " "Info: Total interconnect delay = 4.008 ns ( 79.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.025 ns" { SD[15] SD[15]~16 PB[15]~reg0feeder PB[15]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.025 ns" { SD[15] {} SD[15]~16 {} PB[15]~reg0feeder {} PB[15]~reg0 {} } { 0.000ns 0.000ns 4.008ns 0.000ns } { 0.000ns 0.809ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { clk clk~clkctrl PB[15]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { clk {} clk~combout {} clk~clkctrl {} PB[15]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.025 ns" { SD[15] SD[15]~16 PB[15]~reg0feeder PB[15]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.025 ns" { SD[15] {} SD[15]~16 {} PB[15]~reg0feeder {} PB[15]~reg0 {} } { 0.000ns 0.000ns 4.008ns 0.000ns } { 0.000ns 0.809ns 0.053ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Peak virtual memory: 159 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 06 18:02:48 2009 " "Info: Processing ended: Mon Apr 06 18:02:48 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Info: Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}