prev_cmp_hw1.tan.qmsg

一个模拟ISA界面的简易小程式

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } } { "d:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register IOCS16~reg0 holdIOW 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"IOCS16~reg0\" and destination register \"holdIOW\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.978 ns + Longest register register " "Info: + Longest register to register delay is 0.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IOCS16~reg0 1 REG LCFF_X19_Y19_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y19_N1; Fanout = 4; REG Node = 'IOCS16~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IOCS16~reg0 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.746 ns) 0.978 ns holdIOW 2 REG LCFF_X19_Y19_N25 3 " "Info: 2: + IC(0.232 ns) + CELL(0.746 ns) = 0.978 ns; Loc. = LCFF_X19_Y19_N25; Fanout = 3; REG Node = 'holdIOW'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.978 ns" { IOCS16~reg0 holdIOW } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.746 ns ( 76.28 % ) " "Info: Total cell delay = 0.746 ns ( 76.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.232 ns ( 23.72 % ) " "Info: Total interconnect delay = 0.232 ns ( 23.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.978 ns" { IOCS16~reg0 holdIOW } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "0.978 ns" { IOCS16~reg0 {} holdIOW {} } { 0.000ns 0.232ns } { 0.000ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.458 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 52 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.618 ns) 2.458 ns holdIOW 3 REG LCFF_X19_Y19_N25 3 " "Info: 3: + IC(0.643 ns) + CELL(0.618 ns) = 2.458 ns; Loc. = LCFF_X19_Y19_N25; Fanout = 3; REG Node = 'holdIOW'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk~clkctrl holdIOW } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.89 % ) " "Info: Total cell delay = 1.472 ns ( 59.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.986 ns ( 40.11 % ) " "Info: Total interconnect delay = 0.986 ns ( 40.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { clk clk~clkctrl holdIOW } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.458 ns" { clk {} clk~combout {} clk~clkctrl {} holdIOW {} } { 0.000ns 0.000ns 0.343ns 0.643ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.458 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 52 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.618 ns) 2.458 ns IOCS16~reg0 3 REG LCFF_X19_Y19_N1 4 " "Info: 3: + IC(0.643 ns) + CELL(0.618 ns) = 2.458 ns; Loc. = LCFF_X19_Y19_N1; Fanout = 4; REG Node = 'IOCS16~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk~clkctrl IOCS16~reg0 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.89 % ) " "Info: Total cell delay = 1.472 ns ( 59.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.986 ns ( 40.11 % ) " "Info: Total interconnect delay = 0.986 ns ( 40.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { clk clk~clkctrl IOCS16~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.458 ns" { clk {} clk~combout {} clk~clkctrl {} IOCS16~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.643ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { clk clk~clkctrl holdIOW } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.458 ns" { clk {} clk~combout {} clk~clkctrl {} holdIOW {} } { 0.000ns 0.000ns 0.343ns 0.643ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { clk clk~clkctrl IOCS16~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.458 ns" { clk {} clk~combout {} clk~clkctrl {} IOCS16~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.643ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.978 ns" { IOCS16~reg0 holdIOW } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "0.978 ns" { IOCS16~reg0 {} holdIOW {} } { 0.000ns 0.232ns } { 0.000ns 0.746ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { clk clk~clkctrl holdIOW } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.458 ns" { clk {} clk~combout {} clk~clkctrl {} holdIOW {} } { 0.000ns 0.000ns 0.343ns 0.643ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { clk clk~clkctrl IOCS16~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.458 ns" { clk {} clk~combout {} clk~clkctrl {} IOCS16~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.643ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { holdIOW } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { holdIOW {} } {  } {  } "" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "PA\[4\]~reg0 SA\[3\] clk 7.270 ns register " "Info: tsu for register \"PA\[4\]~reg0\" (data pin = \"SA\[3\]\", clock pin = \"clk\") is 7.270 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.662 ns + Longest pin register " "Info: + Longest pin to register delay is 9.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns SA\[3\] 1 PIN PIN_L8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_L8; Fanout = 1; PIN Node = 'SA\[3\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.770 ns) + CELL(0.357 ns) 4.907 ns Equal0~1 2 COMB LCCOMB_X39_Y18_N0 5 " "Info: 2: + IC(3.770 ns) + CELL(0.357 ns) = 4.907 ns; Loc. = LCCOMB_X39_Y18_N0; Fanout = 5; COMB Node = 'Equal0~1'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.127 ns" { SA[3] Equal0~1 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.617 ns) + CELL(0.154 ns) 6.678 ns always0~9 3 COMB LCCOMB_X19_Y19_N20 16 " "Info: 3: + IC(1.617 ns) + CELL(0.154 ns) = 6.678 ns; Loc. = LCCOMB_X19_Y19_N20; Fanout = 16; COMB Node = 'always0~9'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.771 ns" { Equal0~1 always0~9 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.238 ns) + CELL(0.746 ns) 9.662 ns PA\[4\]~reg0 4 REG LCFF_X22_Y4_N19 1 " "Info: 4: + IC(2.238 ns) + CELL(0.746 ns) = 9.662 ns; Loc. = LCFF_X22_Y4_N19; Fanout = 1; REG Node = 'PA\[4\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.984 ns" { always0~9 PA[4]~reg0 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.037 ns ( 21.08 % ) " "Info: Total cell delay = 2.037 ns ( 21.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.625 ns ( 78.92 % ) " "Info: Total interconnect delay = 7.625 ns ( 78.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.662 ns" { SA[3] Equal0~1 always0~9 PA[4]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.662 ns" { SA[3] {} SA[3]~combout {} Equal0~1 {} always0~9 {} PA[4]~reg0 {} } { 0.000ns 0.000ns 3.770ns 1.617ns 2.238ns } { 0.000ns 0.780ns 0.357ns 0.154ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.482 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 52 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.618 ns) 2.482 ns PA\[4\]~reg0 3 REG LCFF_X22_Y4_N19 1 " "Info: 3: + IC(0.667 ns) + CELL(0.618 ns) = 2.482 ns; Loc. = LCFF_X22_Y4_N19; Fanout = 1; REG Node = 'PA\[4\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { clk~clkctrl PA[4]~reg0 } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.31 % ) " "Info: Total cell delay = 1.472 ns ( 59.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 40.69 % ) " "Info: Total interconnect delay = 1.010 ns ( 40.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { clk clk~clkctrl PA[4]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { clk {} clk~combout {} clk~clkctrl {} PA[4]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.662 ns" { SA[3] Equal0~1 always0~9 PA[4]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.662 ns" { SA[3] {} SA[3]~combout {} Equal0~1 {} always0~9 {} PA[4]~reg0 {} } { 0.000ns 0.000ns 3.770ns 1.617ns 2.238ns } { 0.000ns 0.780ns 0.357ns 0.154ns 0.746ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { clk clk~clkctrl PA[4]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { clk {} clk~combout {} clk~clkctrl {} PA[4]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk SD\[0\] OE 7.666 ns register " "Info: tco from clock \"clk\" to destination pin \"SD\[0\]\" through register \"OE\" is 7.666 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.479 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 52 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.618 ns) 2.479 ns OE 3 REG LCFF_X31_Y15_N17 16 " "Info: 3: + IC(0.664 ns) + CELL(0.618 ns) = 2.479 ns; Loc. = LCFF_X31_Y15_N17; Fanout = 16; REG Node = 'OE'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { clk~clkctrl OE } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.38 % ) " "Info: Total cell delay = 1.472 ns ( 59.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 40.62 % ) " "Info: Total interconnect delay = 1.007 ns ( 40.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { clk clk~clkctrl OE } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { clk {} clk~combout {} clk~clkctrl {} OE {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.093 ns + Longest register pin " "Info: + Longest register to pin delay is 5.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns OE 1 REG LCFF_X31_Y15_N17 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y15_N17; Fanout = 16; REG Node = 'OE'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { OE } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.131 ns) + CELL(1.962 ns) 5.093 ns SD\[0\] 2 PIN PIN_C19 0 " "Info: 2: + IC(3.131 ns) + CELL(1.962 ns) = 5.093 ns; Loc. = PIN_C19; Fanout = 0; PIN Node = 'SD\[0\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.093 ns" { OE SD[0] } "NODE_NAME" } } { "CUD.v" "" { Text "H:/Digital Interface HW/hw1/CUD.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.962 ns ( 38.52 % ) " "Info: Total cell delay = 1.962 ns ( 38.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.131 ns ( 61.48 % ) " "Info: Total interconnect delay = 3.131 ns ( 61.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.093 ns" { OE SD[0] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.093 ns" { OE {} SD[0] {} } { 0.000ns 3.131ns } { 0.000ns 1.962ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { clk clk~clkctrl OE } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { clk {} clk~combout {} clk~clkctrl {} OE {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.093 ns" { OE SD[0] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.093 ns" { OE {} SD[0] {} } { 0.000ns 3.131ns } { 0.000ns 1.962ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}