hw1.flow.rpt

一个模拟ISA界面的简易小程式

Flow report for hw1
Mon Apr 06 18:02:47 2009
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------------+-----------------------------------------+
; Flow Status                   ; Successful - Mon Apr 06 18:02:47 2009   ;
; Quartus II Version            ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name                 ; hw1                                     ;
; Top-level Entity Name         ; CUD                                     ;
; Family                        ; Stratix II                              ;
; Met timing requirements       ; Yes                                     ;
; Logic utilization             ; < 1 %                                   ;
;     Combinational ALUTs       ; 31 / 12,480 ( < 1 % )                   ;
;     Dedicated logic registers ; 52 / 12,480 ( < 1 % )                   ;
; Total registers               ; 52                                      ;
; Total pins                    ; 102 / 343 ( 30 % )                      ;
; Total virtual pins            ; 0                                       ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                     ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                          ;
; Total PLLs                    ; 0 / 6 ( 0 % )                           ;
; Total DLLs                    ; 0 / 2 ( 0 % )                           ;
; Device                        ; EP2S15F484C3                            ;
; Timing Models                 ; Final                                   ;
+-------------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 04/06/2009 18:00:08 ;
; Main task         ; Compilation         ;
; Revision Name     ; hw1                 ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                ;
+------------------------------------+-----------------------------+---------------+-------------+----------------+
; Assignment Name                    ; Value                       ; Default Value ; Entity Name ; Section Id     ;
+------------------------------------+-----------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID              ; 53532822897.123901200802856 ; --            ; --          ; --             ;
; PARTITION_COLOR                    ; 16764057                    ; --            ; CUD         ; Top            ;
; PARTITION_NETLIST_TYPE             ; SOURCE                      ; --            ; CUD         ; Top            ;
; TOP_LEVEL_ENTITY                   ; CUD                         ; hw1           ; --          ; --             ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                         ; --            ; --          ; eda_blast_fpga ;
+------------------------------------+-----------------------------+---------------+-------------+----------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:23     ; 1.0                     ; 196 MB              ; 00:00:03                           ;
; Fitter                  ; 00:01:01     ; 1.0                     ; 258 MB              ; 00:00:16                           ;
; Assembler               ; 00:00:45     ; 1.0                     ; 211 MB              ; 00:00:10                           ;
; Classic Timing Analyzer ; 00:00:36     ; 1.0                     ; 145 MB              ; 00:00:01                           ;
; Total                   ; 00:02:45     ; --                      ; --                  ; 00:00:30                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


+---------------------------------------------------------------------------------------+
; Flow OS Summary                                                                       ;
+-------------------------+------------------+------------+------------+----------------+
; Module Name             ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
+-------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis    ; 888tiger-d65d94  ; Windows XP ; 5.1        ; i686           ;
; Fitter                  ; 888tiger-d65d94  ; Windows XP ; 5.1        ; i686           ;
; Assembler               ; 888tiger-d65d94  ; Windows XP ; 5.1        ; i686           ;
; Classic Timing Analyzer ; 888tiger-d65d94  ; Windows XP ; 5.1        ; i686           ;
+-------------------------+------------------+------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off hw1 -c hw1
quartus_fit --read_settings_files=off --write_settings_files=off hw1 -c hw1
quartus_asm --read_settings_files=off --write_settings_files=off hw1 -c hw1
quartus_tan --read_settings_files=off --write_settings_files=off hw1 -c hw1 --timing_analysis_only