hw1.map.rpt

一个模拟ISA界面的简易小程式

; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                          ;
+----------------------------------+-----------------+------------------------+-----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path      ;
+----------------------------------+-----------------+------------------------+-----------------------------------+
; CUD.v                            ; yes             ; User Verilog HDL File  ; H:/Digital Interface HW/hw1/CUD.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 31    ;
; Dedicated logic registers                     ; 52    ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 5     ;
;                                               ;       ;
; Total combinational functions                 ; 31    ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 10    ;
;     -- 5 input functions                      ; 3     ;
;     -- 4 input functions                      ; 13    ;
;     -- <=3 input functions                    ; 5     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 31    ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 63    ;
;                                               ;       ;
; Total registers                               ; 52    ;
;     -- Dedicated logic registers              ; 52    ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 32    ;
;                                               ;       ;
; I/O pins                                      ; 102   ;
; Maximum fan-out node                          ; clk   ;
; Maximum fan-out                               ; 52    ;
; Total fan-out                                 ; 358   ;
; Average fan-out                               ; 1.94  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |CUD                       ; 31 (31)           ; 52 (52)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 102  ; 0            ; |CUD                ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 52    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 50    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; IOCS16~reg0                            ; 4       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 16 bits   ; 32 ALUTs      ; 32 ALUTs             ; 0 ALUTs                ; Yes        ; |CUD|SDout[0]              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Mon Apr 06 17:59:48 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hw1 -c hw1
Info: Found 1 design units, including 1 entities, in source file hw1.bdf
    Info: Found entity 1: hw1
Info: Found 1 design units, including 1 entities, in source file CUD.v
    Info: Found entity 1: CUD
Info: Elaborating entity "CUD" for the top level hierarchy
Info: Implemented 165 device resources after synthesis - the final resource count might be different
    Info: Implemented 53 input pins
    Info: Implemented 33 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 63 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 196 megabytes
    Info: Processing ended: Mon Apr 06 18:00:12 2009
    Info: Elapsed time: 00:00:24
    Info: Total CPU time (on all processors): 00:00:04