hw1.fit.rpt

一个模拟ISA界面的简易小程式

; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                     ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------+
; I/O Assignment Warnings                  ;
+----------+-------------------------------+
; Pin Name ; Reason                        ;
+----------+-------------------------------+
; SD[0]    ; Incomplete set of assignments ;
; SD[1]    ; Incomplete set of assignments ;
; SD[2]    ; Incomplete set of assignments ;
; SD[3]    ; Incomplete set of assignments ;
; SD[4]    ; Incomplete set of assignments ;
; SD[5]    ; Incomplete set of assignments ;
; SD[6]    ; Incomplete set of assignments ;
; SD[7]    ; Incomplete set of assignments ;
; SD[8]    ; Incomplete set of assignments ;
; SD[9]    ; Incomplete set of assignments ;
; SD[10]   ; Incomplete set of assignments ;
; SD[11]   ; Incomplete set of assignments ;
; SD[12]   ; Incomplete set of assignments ;
; SD[13]   ; Incomplete set of assignments ;
; SD[14]   ; Incomplete set of assignments ;
; SD[15]   ; Incomplete set of assignments ;
; PA[0]    ; Incomplete set of assignments ;
; PA[1]    ; Incomplete set of assignments ;
; PA[2]    ; Incomplete set of assignments ;
; PA[3]    ; Incomplete set of assignments ;
; PA[4]    ; Incomplete set of assignments ;
; PA[5]    ; Incomplete set of assignments ;
; PA[6]    ; Incomplete set of assignments ;
; PA[7]    ; Incomplete set of assignments ;
; PA[8]    ; Incomplete set of assignments ;
; PA[9]    ; Incomplete set of assignments ;
; PA[10]   ; Incomplete set of assignments ;
; PA[11]   ; Incomplete set of assignments ;
; PA[12]   ; Incomplete set of assignments ;
; PA[13]   ; Incomplete set of assignments ;
; PA[14]   ; Incomplete set of assignments ;
; PA[15]   ; Incomplete set of assignments ;
; PB[0]    ; Incomplete set of assignments ;
; PB[1]    ; Incomplete set of assignments ;
; PB[2]    ; Incomplete set of assignments ;
; PB[3]    ; Incomplete set of assignments ;
; PB[4]    ; Incomplete set of assignments ;
; PB[5]    ; Incomplete set of assignments ;
; PB[6]    ; Incomplete set of assignments ;
; PB[7]    ; Incomplete set of assignments ;
; PB[8]    ; Incomplete set of assignments ;
; PB[9]    ; Incomplete set of assignments ;
; PB[10]   ; Incomplete set of assignments ;
; PB[11]   ; Incomplete set of assignments ;
; PB[12]   ; Incomplete set of assignments ;
; PB[13]   ; Incomplete set of assignments ;
; PB[14]   ; Incomplete set of assignments ;
; PB[15]   ; Incomplete set of assignments ;
; IOCS16   ; Incomplete set of assignments ;
; clk      ; Incomplete set of assignments ;
; IOW      ; Incomplete set of assignments ;
; SA[4]    ; Incomplete set of assignments ;
; SA[0]    ; Incomplete set of assignments ;
; SA[15]   ; Incomplete set of assignments ;
; SA[11]   ; Incomplete set of assignments ;
; SA[10]   ; Incomplete set of assignments ;
; SA[7]    ; Incomplete set of assignments ;
; SA[2]    ; Incomplete set of assignments ;
; SA[9]    ; Incomplete set of assignments ;
; SA[13]   ; Incomplete set of assignments ;
; SA[12]   ; Incomplete set of assignments ;
; SA[6]    ; Incomplete set of assignments ;
; SA[8]    ; Incomplete set of assignments ;
; SA[14]   ; Incomplete set of assignments ;
; SA[3]    ; Incomplete set of assignments ;
; SA[1]    ; Incomplete set of assignments ;
; SA[5]    ; Incomplete set of assignments ;
; SBHE     ; Incomplete set of assignments ;
; BALE     ; Incomplete set of assignments ;
; IOR      ; Incomplete set of assignments ;
; PC[0]    ; Incomplete set of assignments ;
; PD[0]    ; Incomplete set of assignments ;