hw1.fit.rpt

一个模拟ISA界面的简易小程式

Fitter report for hw1
Mon Apr 06 18:01:16 2009
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. I/O Assignment Warnings
  5. Incremental Compilation Preservation Summary
  6. Incremental Compilation Partition Settings
  7. Incremental Compilation Placement Preservation
  8. Pin-Out File
  9. Fitter Resource Usage Summary
 10. Input Pins
 11. Output Pins
 12. Bidir Pins
 13. I/O Bank Usage
 14. All Package Pins
 15. Output Pin Default Load For Reported TCO
 16. Fitter Resource Utilization by Entity
 17. Delay Chain Summary
 18. Pad To Core Delay Chain Fanout
 19. Control Signals
 20. Global & Other Fast Signals
 21. Non-Global High Fan-Out Signals
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. I/O Rules Summary
 29. I/O Rules Details
 30. I/O Rules Matrix
 31. Fitter Device Options
 32. Operating Settings and Conditions
 33. Estimated Delay Added for Hold Timing
 34. Advanced Data - General
 35. Advanced Data - Placement Preparation
 36. Advanced Data - Placement
 37. Advanced Data - Routing
 38. Fitter Messages
 39. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Fitter Summary                                                          ;
+-------------------------------+-----------------------------------------+
; Fitter Status                 ; Successful - Mon Apr 06 18:01:16 2009   ;
; Quartus II Version            ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name                 ; hw1                                     ;
; Top-level Entity Name         ; CUD                                     ;
; Family                        ; Stratix II                              ;
; Device                        ; EP2S15F484C3                            ;
; Timing Models                 ; Final                                   ;
; Logic utilization             ; < 1 %                                   ;
;     Combinational ALUTs       ; 31 / 12,480 ( < 1 % )                   ;
;     Dedicated logic registers ; 52 / 12,480 ( < 1 % )                   ;
; Total registers               ; 52                                      ;
; Total pins                    ; 102 / 343 ( 30 % )                      ;
; Total virtual pins            ; 0                                       ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                     ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                          ;
; Total PLLs                    ; 0 / 6 ( 0 % )                           ;
; Total DLLs                    ; 0 / 2 ( 0 % )                           ;
+-------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; AUTO                           ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;