mine4.vhd

自己编的VHDL的波形发生器 做信号的可以看看

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mine4 IS 
PORT(clk:IN STD_LOGIC;--时钟输入线
     set,clr,up,down,zu,zd:IN STD_LOGIC;----各个波形特征的调节触发信号 
     posting:IN STD_LOGIC;---任意波形键盘置入信号
     u0,d0,sw:IN STD_LOGIC;--方波A,B的切换SW，和方波B的幅度调节按键
     ss:IN STD_LOGIC_VECTOR(3 downto 0);----档位选择信号
     sss:IN STD_LOgic_VECTOR(4 DOWNTO 0);---波形选择信号
     data3,data2,data1,data0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--BCD码输入
     p180:OUT STD_LOgic;--预留接口
     lcd:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);---显示输出
     shift:OUT STD_LOgic_VECTOR(3 DOWNTO 0);---位码输出
     dd,a:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));---波形，幅度数据输出
END mine4;

ARCHITECTURE behave OF mine4 IS
subtype word is STD_LOGIC_VECTOR(7 downto 0);
type unit is array(63 downto 0)of word;
signal ram:unit;
signal qqq:integer range 0 to 250000000;--计数分频
signal qq:integer range 0 to 78125000;--计数分频
signal tmp:integer range 0 to 9999;
signal coun:integer range 0 to 78125000;
signal coun0:integer range 0 to 250000000;
signal b:integer range 0 to 78125000;
signal c:integer range 0 to 50000000;
signal z,con:integer range 0 to 63;
signal f:std_logic_vector(7 downto 0);
signal amp,amp0,d:std_logic_vector(7 downto 0);
signal bcd0,bcd1,bcd2,bcd3:integer range 0 to 9;
signal bcd01,bcd11,bcd21,bcd31:integer range 0 to 9;
signal bcd00,bcd10,bcd20,bcd30:integer range 0 to 9;
signal y:integer range 0 to 9;
signal addr:integer range 0 to 63;
begin
----qq信号对应SW=0时的档位选择信号SS，实现方波A和其他三种波形的频率预置
qq<=781250 when ss="1000" else---分频 输出频率（f0=f/预置数）
    7812500 when ss="0100" else
    78125000 when ss="0010" else
    78125;
-----qqq信号对应SW=1时档位信号SS,实现方波B的频率预置
qqq<=500000 when ss="1000" else--分频 输出的频率
     5000000 when ss="0100" else
     50000000 when ss="0010" else
     5000;

process(clk)
-----此进程分别描述了各种波形的频率，幅度（方波A的占空比）调节以及各种波形的任意线性叠加等--------
variable count4:integer range 0 to 6250000;    
variable count:integer range 0 to 78125000;  
variable count3:integer range 0 to 250000000;  
variable count1:integer range 0 to 12500000;  
variable count0:integer range 0 to 3249999;  
variable ddd:std_logic_vector(9 downto 0);  
variable dd0,dd1,dd2,dd3,dd4:integer range 0 to 255;  
variable adr:integer range 0 to 63;--63个采样点
begin
if rising_edge(clk)then
 if posting='1' then--任意波形信号键
  if count4=6249999 then count:=0;---分频
     adr:=conv_integer(data3)*10+conv_integer(data2);--存储单位地址
    if adr<64 then
      if set='1' then ram(adr)<=conv_std_loigc_vector((conv_integer(data1)*10+conv_integer(data0)*2,8)--对置入的任意波形进行储存
      elsif clr='1' then adr:=0;--存储器所有单元清零
      for i in 0 to 63 loop;---循环取存放到ram单元里的采样点
      ram(i)<=(other=>'0');
      end loop;
     end if;
    end if;
  else count4:=count4+1;--不到计数
  end if;
else
  if set='1' then coun<=0;b<=0;coun<=0;c<=0;z<=31;amp0<="01111111";