updcnt7_25um.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : updcnt7_25um.vhd
-- Design Date: 21 Mar 2000
-- Creation Date: Mon May 06 13:42:48 2002
-- Created By SpDE Version: SpDE 9.3 Alpha Build3
-- Author: Ed Bezeg, Brian Faith, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description: This is the counter for generating the read
-- and write addresses in the FIFOs.
------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- inputs: up,down,clk,rst
-- outputs: =q[6:0]=

entity updcnt7_25um is
   port (up : in std_logic;
         down : in std_logic;
         clk : in std_logic;
         rst : in std_logic;
         q : out std_logic_vector (6 downto 0));
end updcnt7_25um;

-- This is the counter for generating the read adderss
-- and write addresses 
architecture arch of updcnt7_25um is
signal q_reg : std_logic_vector (6 downto 0);
signal ctrl : std_logic_vector (1 downto 0);

begin
q <= q_reg after 1 ns;
ctrl(1 downto 0) <= (up & down) after 1 ns;

main : process (clk, rst)
   begin
      if (rst = '1') then
         q_reg <= "0000000" after 1 ns;
      elsif Rising_Edge(clk) then
         case ctrl is
            when "00" => q_reg <= q_reg after 1 ns;
            when "01" => q_reg <= q_reg - '1' after 1 ns;
            when "10" => q_reg <= q_reg + '1' after 1 ns;
            when "11" => q_reg <= q_reg after 1 ns;
            when others => q_reg <= "XXXXXXX" after 1 ns;
         end case;
      else
         q_reg <= q_reg after 1 ns;
      end if;
   end process;
end arch;