cardbus_5632.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

	tests_passed := tests_passed + passed;

--	caudio_test(mst_req, mst_resp, tb_CAUDIO, tb_BAM, tb_PWM);
 	caudio_test(address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK,tb_CAUDIO, tb_BAM, tb_PWM, passed);

	tests_passed := tests_passed + passed;

 	cclkrun_test(address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK,tb_CCLKRUN_n, tb_clk_resume, tb_clk_stopped, passed);

	tests_passed := tests_passed + passed;

	-- CBLOCK TEST PORTION BEFORE FORK AND JOIN
   	j := 0;
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] START OF CBLOCK_N TEST"));
	writeline(output, outline);

	-- TEST CASES
	-- signal lock xfer, check lock detect
	-- access as owner, check result.
	-- access by non owner, check result
	-- signal unlock, check result


	-- Test Locked Transfer - Test 1
	-- unlocked, and not target of access
	-- should not respond to access
	
	-- unlock and check results
	-- target should be unnlocked and owner access should be deasserted	
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("]Test Locked Transfer - Test #1 - unlocked, not target of access.")); 
	write(outline, string'("protocol error expected."));
	writeline(output, outline);

	address_reg <= x"00000000AB000000";
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,master1_be_array,master1_data_array,CLK);

	-- target should be unlocked and owner access deasserted
	if (tb_locked = '0' and tb_owner_access = '0') then
		write(outline, string'("CBLOCK_N Test #1 - Passed..."));
		writeline(output, outline);
	   	j := j + 1;
	end if;

	-- Test Locked Transfer - Test 2
	-- unlocked, target of access but do not lock
	-- locked and owner_access should be deasserted

	-- unlock and check results
	-- target should be unnlocked and owner access should be deasserted	
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("]Test Locked Transfer - Test #2 - unlocked, target of access, but do not lock."));
	writeline(output, outline);


   	address_reg <= x"00000000CB000300";
   	data_reg <= x"FFFFFFFFFFFFFFFF";
		pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,master1_be_array,master1_data_array,CLK);

	-- target should be unlocked and owner access deasserted
	if (tb_locked = '0' and tb_owner_access = '0') then
		write(outline, string'("CBLOCK_N Test #2 - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	-- 	Test Locked Transfer - Test 3
	-- unlocked, access exclusively
	-- locked and owner_access should both be asserted	

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("]Test Locked Transfer - Test #3 - unlocked, access exclusively."));
	writeline(output, outline);

	wait until rising_edge(CLK);
	cblock_test3_go <= '1';

	-- do any memory access
   	address_reg <= x"00000000CB000300";
   	data_reg <= x"FFFFFFFFFFFFFFFF";
	   	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);
	-- wait for one clock cycle

--	wait until rising_edge(CLK);
	cblock_test3_go <= '0';
  -- 		for j in 1 to 10 loop
  -- 		wait until rising_edge(CLK);
  -- 		end loop;

	if tb_locked = '1' then
		write(outline, string'("CBLOCK_N Test #3a - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	wait until (CLK'event and CLK = '1');

	if tb_owner_access = '1' then
		write(outline, string'("CBLOCK_N Test #3b - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	-- 	Test Locked Transfer - Test 4
	-- locked, access by owner
	-- locked should be asserted and owner_access should be asserted

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("]Test Locked Transfer - Test #4 - locked, continued access by owner."));
	writeline(output, outline);

	wait until rising_edge(CLK);
	cblock_test4_go <= '1';

	-- do any memory access
   	address_reg <= x"00000000CB000300";
   	data_reg <= x"FFFFFFFFFFFFFFFF";
	   	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);
	-- wait for one clock cycle

	wait until rising_edge(CLK);
	cblock_test4_go <= '0';

	if tb_locked = '1' then
		write(outline, string'("CBLOCK_N Test #4a - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	wait until (CLK'event and CLK = '1');

	if tb_owner_access = '1' then
		write(outline, string'("CBLOCK_N Test #4b - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	-- 	Test Locked Transfer - Test 5
	-- locked, access by non-owner
	-- locked should be asserted and owner_access should not be asserted

	-- do another memory access
	-- target should remained locked and owner_access should be 0					

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("]Test Locked Transfer - Test #5 - locked, access by non-owner"));
	writeline(output, outline);

	-- do any memory access
	-- access by non-owner is accomplished by keeping the CBLOCK_n signal asserted while doing access
	-- the owner would toggle the CBLOCK_n to continue access where as non-owners can't
   	address_reg <= x"00000000CB000300";
   	data_reg <= x"FFFFFFFFFFFFFFFF";
	   	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

	if tb_locked = '1' then
		write(outline, string'("CBLOCK_N Test #5a - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	wait until (CLK'event and CLK = '1');

	if tb_owner_access = '0' then
		write(outline, string'("CBLOCK_N Test #5b - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	-- 	Test Locked Transfer - Test 6
	-- locked, not target of access
	-- locked should be asserted and owner_access should not be asserted

	-- target should be locked and owner_access should be 0					

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("]Test Locked Transfer - Test #6 - locked, not target of access."));
	write(outline, string'("protocol error expected."));
	writeline(output, outline);

	-- do any memory access, not in BAR0 or BAR5 
   	address_reg <= x"00000000AB000000";
   	data_reg <= x"FFFFFFFFFFFFFFFF";
	   	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

	if tb_locked = '1' then
		write(outline, string'("CBLOCK_N Test #6a - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	wait until (CLK'event and CLK = '1');

	if tb_owner_access = '0' then
		write(outline, string'("CBLOCK_N Test #6b - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;
	
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] END OF CBLOCK_N TEST - "));
	write(outline, integer'image(j));
	write(outline, string'(" out of 10 tests passed."));
	writeline(output, outline);

	tests_passed := tests_passed + j;

 	cis_readback_test(address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK,passed);

	tests_passed := tests_passed + passed;

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] END OF CARDBUS_WRAPPER TEST - "));
	write(outline, integer'image(tests_passed));
	write(outline, string'(" out of 43 TOTAL TESTS passed."));
	writeline(output, outline);


try_5_board_speeds: for h in 1 to 5 loop

	case (h) is
	   when 1 => board_clock_val := "0100"; clk_string := "28 MHz";
	   when 2 => board_clock_val := "0110"; clk_string := "42 MHz";
	   when 3 => board_clock_val := "0011"; clk_string := "56 MHz";
	   when 4 => board_clock_val := "0000"; clk_string := "70 MHz";
	   when 5 => board_clock_val := "0010"; clk_string := "84 MHz";
	end case;

   -- reset the board and set the current clock speed
   address_reg <= x"00000000ffbe010C";					-- start at offset x10c : Status Register
   master1_data_array(0) <= x"00000000";                -- resets the board
   master1_data_array(1) <= x"00000000";                -- dummy write - no affect
   master1_data_array(2) <= x"0000000" & board_clock_val; -- sets a new clock value

   pci_access(address_reg,data_reg,MEM_WRITE,x"FF",3,0,0,0,'0','0',
              master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
              master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
              master1_quiet,master1_be_array,master1_data_array,CLK);

   --  DMA transfer of 64 DWORDs
   address_reg <= x"00000000ffbe0100";	 -- start at offset x100 : DMA Size Register
   master1_data_array(0) <= x"00400040"; -- 64 dwords read and write
   master1_data_array(1) <= x"04444400"; -- write address: 0x11111000 shifted right two bits
   master1_data_array(2) <= x"04444000"; -- read address: 0x11110000 shifted right two bits
   master1_data_array(3) <= x"41000100"; -- enable read and write dmas

   pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,0,0,0,'0','0',
              master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
              master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
              master1_quiet,master1_be_array,master1_data_array,CLK);

   address_reg <= x"00000000ffbe010C";  -- start at offset x100 : DMA Size Register
   data_reg <= x"0000000040000000";		-- this value would indicate that the DMA is done

   wait_for_dma_end: for i in 1 to 20 loop
   		for j in 1 to 20 loop
   		wait until rising_edge(CLK);
   		end loop;
	   	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,0,0,0,'0','1',
	              master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	              master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	              master1_quiet,master1_be_array,master1_data_array,CLK);
	   	if (master1_pass = '1') then
	   		exit wait_for_dma_end;
	   	end if;
   	end loop;	

	if (master1_pass = '0') then
		--report "DMA Error Occurred - DMA Status Code Returned: " & integer'image(to_integer(unsigned(master1_last_data(31 downto 0))));
		write(outline, string'("["));
		write(outline, now);
		write(outline, string'("] DMA Error Occurred - DMA Status Code Returned: "));
		write(outline, integer'image(to_integer(unsigned(master1_last_data(31 downto 0)))));
		writeline(output, outline);
	else
		--report "64 DWORD Read and Write DMA Succeeded, Board Speed = " & clk_string ;
		write(outline, string'("["));
		write(outline, now);
		write(outline, string'("] 64 DWORD Read and Write DMA Succeeded, Board Speed = "));
		write(outline, clk_string);
		writeline(output, outline);
	end if;

   end loop;

	byte_enable_test (address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK);

	pci_cmd_test (address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK);

  --	pci_comp (address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
	--		  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
	  --		  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
		--	  master1_addr, master1_command, master1_dword_count,
		 --	  master1_initial_data_delay, master1_next_data_delay,
		  --	  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			--  master1_be_array, master1_data_array, CLK);

SIM_END <= TRUE;

wait;

end process;


end t_arch;