cardbus_5632.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

	clock_loop: loop 
		wait for HalfCyclePCI;
		CLK <= not CLK;
		if (SIM_END) then exit clock_loop;
			end if;
	end loop;
	wait;
end process;

pci_reset_proc: process is
    variable i : integer;
begin
	REQ64N <= '1';  --    REQ64N inactive during reset (32-bit bus only)
    RSTN <= '0';    --    Assert reset
	for i in 1 to 20 loop
		wait until (CLK'event and CLK='1');
	end loop;
	wait until (CLK'event and CLK='1');
	wait for 160 ns;
	wait until (CLK'event and CLK='1');
	RSTN <= '1' after 4 ns;             --  Go out of reset
	wait until (CLK'event and CLK='1');
	wait;
end process;

-- CBLOCK test #3 and 4
-- part of the CBLOCK test suite
-- see the verilog equivalent in cardbus_wrapper.tf
-- for more details

cblock_test : process (CLK, RSTN) is
begin
	if (RSTN = '0') then
		-- initialize the state machine that controls the CBLOCK signal
		cblock_test3_state <= "000";
		cblock_test4_state <= "000";
		cblock_test3_stop <= '0';
		cblock_test4_stop <= '0';
		tb_CBLOCK_n <= '1';
	elsif CLK'event and CLK = '1' then
		if cblock_test3_go = '1' and cblock_test3_stop = '0' then
			-- if the go flag for test #3 is detected, transition the
			-- state machine to "011" to add a delay in setting the
			-- CBLOCK_n to 0 to match with the timing of the pci_access
			-- in the main simulation block

			-- this is included so that these two processes may run
			-- concurrently, like in a fork join statement in verilog

			-- a stop flag is included (cblock_test3_stop) so that the state
			-- transition will stop after 1 iteration

			case cblock_test3_state is
				when "000" => 	cblock_test3_state <= "001"; 
				when "001" => 	cblock_test3_state <= "010";
				when "010" =>  	cblock_test3_state <= "011";
				when "011" => 	cblock_test3_state <= "000";
								cblock_test3_stop <= '1';			
				when others => 	cblock_test3_state <= "000";
			end case;

		elsif cblock_test4_go = '1' and cblock_test4_stop = '0' then
			-- similar to test #3, these state transitions are added so
			-- the CBLOCK_n signal can be set a the desired time
			-- concurrently with the pci_access
			case cblock_test4_state is
				when "000" =>	cblock_test4_state <= "001";
				when "001" =>	cblock_test4_state <= "010";
				when "010" =>	cblock_test4_state <= "011";
				when "011" => 	cblock_test4_state <= "000";
								cblock_test4_stop <= '1';
--				when "000" =>																	
				when others => cblock_test4_state <= "000";
			end case;					
		end if;

	elsif CLK'event and CLK = '0' then
		-- toggle CBLOCK_n signal 
		if cblock_test3_state = "011" then
			tb_CBLOCK_n <= '0';
		elsif cblock_test4_state = "001" then
			tb_CBLOCK_n <= '1';
		elsif cblock_test4_state = "011" then
			tb_CBLOCK_n <= '0';
   		elsif cblock_test3_stop = '1' and cblock_test4_stop = '1' and cblock_test_stop = '1' then
			tb_CBLOCK_n <= '1'; -- CBLOCK tests completed so return signal to deasserted state
		end if;				
	end if;
end process;



-- instantiate the CIS

	CIS_1 : CIS
		port map (
			pad_CIS_ADR => pad_CIS_ADR,
			pad_CIS_data => pad_CIS_data
			);

-- instantiate the clock generator

	clk_gen_1 : clk_gen 
		port map (
					s0 => s0,
					s1 => s1,
					lclk => lclk,
					stop => SIM_END
			 	 );

	-- instantiate the IDT FIFO

	idt_fifo_1 : idt_fifo
			port map (
				  lad => lad,
				  pae_n => pae_n,
				  paf_n => paf_n,
				  or_n => or_n,
				  ir_n => ir_n,
				  hf_n => hf_n,
				  fs => '0',
				  fwft => '1',
				  ld => ld,
				  rt => '1',
				  mrs => mrs,
				  prs => '1',
				  ren => ren,
				  wen => wen,
				  oe => oe,
				  lclk => lclk
			     );

---------------------------------
-- The main simulation process --
---------------------------------

Main_Simulation: process is
	variable h,i,j : integer;
	variable tests_passed : integer;
	variable clk_string : string(1 to 6);
	variable board_clock_val : std_logic_vector(3 downto 0);
	variable outline : line;
begin
	tests_passed := 0;
--  	tb_CCLKRUN_n <= tb_clkrun_n when (tb_clkrun_oe = '1') else 'Z';

	--initialize protocol checker
	SIM_END <= FALSE;
	Clear_Disconnect <= '0';
	Set_Master_Abort <= '1';
	Clear_SERR <= '0';
	Clear_PERR <= '0'; 
	Status <= '0';

	--initialize simulation target
    target1_RANDOMVAL <= 23;
    target1_DEVICE_SPEED <= 2;
    target1_BASE_ADDRESS <= x"0000000011110000";
    target1_STOP_COUNT <= 5;
    target1_STOP_ENABLE <= '0';
    target1_WAITSTATES_ENABLE <= '0';
    target1_VARIABLE_WAITS <= '0';
    target1_MAX_WAITS <= 8;
    target1_MIN_WAITS <= 0;
    target1_INITIAL_WAITS <= 1;
    target1_SUBSEQUENT_WAITS <= 2;
    target1_STOP_WAITS <= 5;
    target1_RETRY_COUNT <= 2;
    target1_ENABLE_RETRY_COUNT <= '0';
    target1_WRONG_PAR <= '0';
    target1_PERR_ASSERT <= '0';
    target1_TARGET_ABORT <= '0';


	-- ct initialize CardBus inputs
	tb_wp <= '0';
	tb_ready <= '0';
	tb_bvd <= "00";
	tb_gwake <= '0';
	tb_intr <= '0';
	tb_clk_resume <= '0';
	tb_BAM <= '0';
	tb_PWM <= '0';
--	tb_CBLOCK_n <= '1';
	tb_CCLKRUN_n <= '0';
	cblock_test3_go <= '0';
	cblock_test4_go <= '0';

    -- initialize simulation master
    -- (this must be done before first call to pci_access)
	master1_start_bit <= '0'; 
--	master2_start_bit <= '0'; 
    -- initialize target_bar signal for pci_comp procedure
	target_bar <= x"00000000ffbe0000";

	-- wait for reset to settle
	wait until (RSTN'event and RSTN = '1');
	for i in 1 to 10 loop
		wait until (CLK'event and CLK='1');
	end loop;


	-- pci_access procedure
	--
	--              address : IN Destination address of access
    --                 data : IN write/expected data for one quadword transactions (see note)
    --          pci_command : IN The PCI Command to be used for the transfer
    --          byte_enable : IN write/expected byte enables for one quadWord transactions (see note)
    --          dword_count : IN The number of dwords to transfer
    --   initial_waitstates : IN waitstates to insert before 1st IRDYN assertion
    --subsequent_waitstates : IN waitstates to insert after each data phase
	--     bad_parity_phase : IN 0 to disable, sets transfer for bad parity assertion
    --                64bit : IN 1 for a 64-bit master, 0 for a 32-bit master
	--                quiet : IN 0 to issue error if target reads don't match expected data
	--            start_bit : OUT signal passed to simulation master
	--             done_bit : IN signal passed from simulation master
	--                 addr : OUT signal passed to simulation master
	--              command : OUT signal passed to simulation master
	--          dword_count : OUT signal passed to simulation master
	--   initial_data_delay : OUT signal passed to simulation master
	--      next_data_delay : OUT signal passed to simulation master
	--     bad_parity_phase : OUT signal passed to simulation master
	--               m64bit : OUT signal passed to simulation master
	--               mquiet : OUT signal passed to simulation master
	--             be_array : OUT array passed to simulation master
	--           data_array : OUT array passed to simulation master
	--                  CLK : IN 
	--
	-- NOTE: For multi-quadword transactions, be_array and data_array must be initialized
	--       with the appropriate write data for writes, or expected data for reads.

--  Read QuickPCI configuration space
master1_be_array(0) <= "1111";
master1_be_array(1) <= "1111";
master1_be_array(2) <= "1111";
master1_be_array(3) <= "1111";
master1_be_array(4) <= "1111";
address_reg  <= x"0000000000000000";
data_reg <= x"0000000000000000";

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",4,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


--  change QuickPCI BAR
address_reg <= x"0000000000000010";
data_reg <= x"FFFFFFFFFFFFFFFF";

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",1,1,1,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",1,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


data_reg <= x"00000000ffbe0000";

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",1,1,1,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


pci_access(address_reg,data_reg,CONFIG_READ,x"FF",1,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

--  ct added BAR5
address_reg <= x"0000000000000024";
data_reg <= x"FFFFFFFFFFFFFFFF";

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",1,1,1,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",1,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


data_reg <= x"00000000CB000000";

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",1,1,1,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


pci_access(address_reg,data_reg,CONFIG_READ,x"FF",1,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


--  enable and check QuickPCI memory space and enable bus mastering
address_reg <= x"0000000000000004";
data_reg <= x"0000000000000146";

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",1,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);


pci_access(address_reg,data_reg,CONFIG_READ,x"03",1,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

--  write and check QuickPCI LED register

address_reg <= x"00000000ffbe0118";
data_reg <= x"00000000000001A5";

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

pci_access(address_reg,data_reg,MEM_READ,x"FF",1,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

--  set QuickPCI LEDs to show status of FIFOs

address_reg <= x"00000000ffbe0118";
data_reg <= x"0000000000000000";

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
           master1_quiet,master1_be_array,master1_data_array,CLK);

-- ct added test bench for cardbus
-- test suite include tests for : CSTSCHG, CINT, CAUDIO#, CCLKRUN#, CBLOCK#, CIS read back
--cardbus_wrapper(mst_req, mst_resp, tb_CAUDIO, tb_BAM, tb_PWM);
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] START OF CARDBUS_WRAPPER TEST"));
	writeline(output, outline);

	cstschg_test(address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK, 
			  tb_CSTSCHG, tb_wp, tb_ready, tb_bvd, tb_gwake, tb_intr, passed);

 	cint_test(address_reg, data_reg, target_bar, Master_Abort, Set_Master_Abort,
			  SERRN_Detected, PERRN_Detected, Clear_SERR, Clear_Disconnect,
			  Disconnect_Detected, Clear_PERR, master1_start_bit, master1_done_bit,
			  master1_addr, master1_command, master1_dword_count,
			  master1_initial_data_delay, master1_next_data_delay,
			  master1_bad_parity_phase, master1_m64bit, master1_quiet,
			  master1_be_array, master1_data_array, CLK, tb_intr, tb_CINT_n, passed);